Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	314814970	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1233	1233	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	314814970	0	0
T1	175864	2227	0	0
T2	962508	669177	0	0
T3	203054	46159	0	0
T7	8573	2086	0	0
T19	17206	149	0	0
T26	300296	70958	0	0
T38	26508	1374	0	0
T39	605266	620944	0	0
T40	725407	496921	0	0
T41	624857	641222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233	1233	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	630941956	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1233	1233	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	630941956	0	0
T1	175864	2227	0	0
T2	962508	301207	0	0
T3	203054	46159	0	0
T7	8573	2086	0	0
T19	17206	149	0	0
T26	300296	70958	0	0
T38	26508	1374	0	0
T39	605266	620944	0	0
T40	725407	223700	0	0
T41	624857	641222	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	175864	175773	0	0
T2	962508	962498	0	0
T3	203054	202965	0	0
T7	8573	8519	0	0
T19	17206	17129	0	0
T26	300296	300234	0	0
T38	26508	26424	0	0
T39	605266	605259	0	0
T40	725407	725399	0	0
T41	624857	624851	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233	1233	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T26	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0