Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	23730	0	0
entropy_period_rd_A	2147483647	1848	0	0
intr_enable_rd_A	2147483647	2682	0	0
prefix_0_rd_A	2147483647	2171	0	0
prefix_10_rd_A	2147483647	2344	0	0
prefix_1_rd_A	2147483647	2350	0	0
prefix_2_rd_A	2147483647	2168	0	0
prefix_3_rd_A	2147483647	2225	0	0
prefix_4_rd_A	2147483647	2268	0	0
prefix_5_rd_A	2147483647	2160	0	0
prefix_6_rd_A	2147483647	2121	0	0
prefix_7_rd_A	2147483647	2273	0	0
prefix_8_rd_A	2147483647	2107	0	0
prefix_9_rd_A	2147483647	2287	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23730	0	0
T72	188250	20321	0	0
T128	0	36	0	0
T141	0	198	0	0
T142	0	1	0	0
T143	0	1	0	0
T151	0	138	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	24277	0	0	0
T158	1026	0	0	0
T159	143200	0	0	0
T160	102872	0	0	0
T161	751005	0	0	0
T162	204280	0	0	0
T163	710100	0	0	0
T164	10292	0	0	0
T165	90159	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1848	0	0
T99	6088	31	0	0
T100	2833	9	0	0
T101	124894	125	0	0
T108	10896	30	0	0
T153	8438	10	0	0
T154	4851	9	0	0
T172	1958	9	0	0
T173	2255	1	0	0
T174	3015	5	0	0
T175	5451	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2682	0	0
T99	6088	19	0	0
T100	2833	5	0	0
T101	124894	277	0	0
T108	10896	109	0	0
T153	8438	27	0	0
T154	4851	4	0	0
T172	1958	14	0	0
T173	2255	1	0	0
T174	3015	10	0	0
T175	5451	4	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T99	6088	25	0	0
T100	2833	7	0	0
T101	124894	236	0	0
T108	10896	41	0	0
T153	8438	13	0	0
T154	4851	11	0	0
T172	1958	7	0	0
T174	3015	8	0	0
T175	5451	11	0	0
T176	11422	23	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2344	0	0
T99	6088	33	0	0
T101	124894	271	0	0
T108	10896	53	0	0
T153	8438	24	0	0
T154	4851	14	0	0
T172	1958	6	0	0
T173	2255	9	0	0
T174	3015	10	0	0
T175	5451	16	0	0
T176	11422	29	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2350	0	0
T99	6088	33	0	0
T100	2833	9	0	0
T101	124894	257	0	0
T108	10896	58	0	0
T153	8438	18	0	0
T154	4851	5	0	0
T172	1958	9	0	0
T174	3015	12	0	0
T175	5451	11	0	0
T176	11422	52	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2168	0	0
T99	6088	34	0	0
T101	124894	243	0	0
T103	12134	75	0	0
T108	10896	33	0	0
T153	8438	17	0	0
T154	4851	5	0	0
T172	1958	4	0	0
T174	3015	5	0	0
T175	5451	21	0	0
T176	11422	36	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2225	0	0
T99	6088	16	0	0
T100	2833	12	0	0
T101	124894	239	0	0
T108	10896	47	0	0
T153	8438	9	0	0
T154	4851	14	0	0
T172	1958	6	0	0
T174	3015	5	0	0
T175	5451	12	0	0
T176	11422	28	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2268	0	0
T99	6088	22	0	0
T100	2833	5	0	0
T101	124894	290	0	0
T108	10896	35	0	0
T153	8438	7	0	0
T154	4851	5	0	0
T173	2255	7	0	0
T174	3015	3	0	0
T175	5451	12	0	0
T176	11422	25	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2160	0	0
T99	6088	32	0	0
T100	2833	10	0	0
T101	124894	267	0	0
T108	10896	20	0	0
T153	8438	9	0	0
T154	4851	6	0	0
T172	1958	8	0	0
T173	2255	2	0	0
T174	3015	10	0	0
T175	5451	13	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2121	0	0
T99	6088	24	0	0
T100	2833	1	0	0
T101	124894	272	0	0
T108	10896	23	0	0
T153	8438	15	0	0
T154	4851	6	0	0
T172	1958	1	0	0
T173	2255	6	0	0
T174	3015	12	0	0
T175	5451	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2273	0	0
T99	6088	36	0	0
T100	2833	4	0	0
T101	124894	248	0	0
T108	10896	50	0	0
T153	8438	20	0	0
T154	4851	5	0	0
T172	1958	5	0	0
T174	3015	7	0	0
T175	5451	7	0	0
T176	11422	58	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2107	0	0
T99	6088	26	0	0
T101	124894	237	0	0
T103	12134	38	0	0
T108	10896	51	0	0
T153	8438	16	0	0
T154	4851	9	0	0
T156	7784	11	0	0
T172	1958	4	0	0
T174	3015	11	0	0
T176	11422	2	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T99	6088	32	0	0
T100	2833	5	0	0
T101	124894	256	0	0
T108	10896	50	0	0
T153	8438	19	0	0
T154	4851	9	0	0
T172	1958	8	0	0
T173	2255	7	0	0
T174	3015	7	0	0
T175	5451	12	0	0