Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256801216

1

T1

13

T2

10

T3

114029

full_word

180914541

1

T1

163

T2

2

T3

809203

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	437715427	1			T1	176		T2	12		T3	194949
auto[TlIntgErrCmd]	98	1			T118	7		T122	5		T123	2
auto[TlIntgErrData]	104	1			T118	6		T122	3		T123	2
auto[TlIntgErrBoth]	128	1			T118	7		T122	2		T123	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227247315

1

T1

74

T2

1

T3

100988

auto[1]

210468442

1

T1

102

T2

11

T3

939608

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157257362	1			T1	6		T3	687904		T6	55991
auto[TlIntgErrNone]	partial	auto[1]	99543552	1			T1	7		T2	10		T3	452387
auto[TlIntgErrNone]	full_word	auto[0]	69989780	1			T1	68		T2	1		T3	321982
auto[TlIntgErrNone]	full_word	auto[1]	110924733	1			T1	95		T2	1		T3	487221
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T118	6		T122	2		T123	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T118	1		T122	2		T135	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T176	1		T177	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T122	1		T173	1		T178	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T118	4		T122	2		T123	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T118	2		T135	2		T176	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T123	1		T135	1		T179	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	1		T180	1		T181	2
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T118	5		T123	1		T135	7
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T118	2		T122	2		T123	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T123	2		T181	1		T172	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T135	1		T176	1		T174	1