Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.58	98.75	95.65	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	37725	0	0
entropy_period_rd_A	2147483647	1539	0	0
intr_enable_rd_A	2147483647	2252	0	0
prefix_0_rd_A	2147483647	1213	0	0
prefix_10_rd_A	2147483647	1146	0	0
prefix_1_rd_A	2147483647	1140	0	0
prefix_2_rd_A	2147483647	1168	0	0
prefix_3_rd_A	2147483647	1235	0	0
prefix_4_rd_A	2147483647	1155	0	0
prefix_5_rd_A	2147483647	1121	0	0
prefix_6_rd_A	2147483647	1073	0	0
prefix_7_rd_A	2147483647	1078	0	0
prefix_8_rd_A	2147483647	1273	0	0
prefix_9_rd_A	2147483647	1341	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37725	0	0
T49	228182	34147	0	0
T95	0	8	0	0
T109	0	80	0	0
T120	0	220	0	0
T121	0	164	0	0
T122	0	1	0	0
T123	0	2	0	0
T130	0	153	0	0
T134	0	8	0	0
T135	0	4	0	0
T136	151190	0	0	0
T137	330363	0	0	0
T138	235067	0	0	0
T139	23174	0	0	0
T140	156639	0	0	0
T141	331466	0	0	0
T142	146658	0	0	0
T143	359036	0	0	0
T144	168679	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1539	0	0
T93	3901	6	0	0
T96	3754	8	0	0
T101	3205	17	0	0
T102	13545	40	0	0
T122	11145	27	0	0
T123	19283	56	0	0
T135	28982	125	0	0
T156	2917	10	0	0
T157	5664	36	0	0
T158	9340	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2252	0	0
T93	3901	16	0	0
T96	3754	17	0	0
T101	3205	24	0	0
T122	11145	18	0	0
T123	19283	89	0	0
T156	2917	8	0	0
T157	5664	30	0	0
T159	1730	9	0	0
T160	793	15	0	0
T161	1177	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1213	0	0
T93	3901	12	0	0
T96	3754	14	0	0
T101	3205	14	0	0
T102	13545	37	0	0
T122	11145	28	0	0
T123	19283	45	0	0
T135	28982	86	0	0
T156	2917	16	0	0
T157	5664	28	0	0
T158	9340	35	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1146	0	0
T93	3901	5	0	0
T96	3754	4	0	0
T101	3205	6	0	0
T102	13545	15	0	0
T122	11145	30	0	0
T123	19283	43	0	0
T156	2917	9	0	0
T157	5664	17	0	0
T158	9340	10	0	0
T159	1730	3	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1140	0	0
T93	3901	14	0	0
T96	3754	6	0	0
T101	3205	18	0	0
T102	13545	28	0	0
T121	6638	3	0	0
T122	11145	31	0	0
T123	19283	28	0	0
T156	2917	9	0	0
T157	5664	2	0	0
T158	9340	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1168	0	0
T93	3901	15	0	0
T96	3754	16	0	0
T101	3205	18	0	0
T102	13545	21	0	0
T122	11145	35	0	0
T123	19283	40	0	0
T135	28982	69	0	0
T156	2917	11	0	0
T157	5664	4	0	0
T158	9340	38	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1235	0	0
T93	3901	4	0	0
T96	3754	17	0	0
T101	3205	9	0	0
T102	13545	26	0	0
T122	11145	28	0	0
T123	19283	40	0	0
T135	28982	77	0	0
T156	2917	7	0	0
T157	5664	9	0	0
T158	9340	20	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1155	0	0
T93	3901	10	0	0
T96	3754	5	0	0
T101	3205	9	0	0
T102	13545	28	0	0
T122	11145	14	0	0
T123	19283	29	0	0
T135	28982	98	0	0
T156	2917	9	0	0
T157	5664	38	0	0
T158	9340	16	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1121	0	0
T93	3901	17	0	0
T96	3754	8	0	0
T101	3205	19	0	0
T102	13545	21	0	0
T122	11145	35	0	0
T123	19283	38	0	0
T135	28982	65	0	0
T156	2917	6	0	0
T157	5664	17	0	0
T158	9340	5	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073	0	0
T93	3901	21	0	0
T96	3754	14	0	0
T101	3205	15	0	0
T102	13545	22	0	0
T122	11145	17	0	0
T123	19283	36	0	0
T135	28982	64	0	0
T156	2917	7	0	0
T158	9340	9	0	0
T162	5477	27	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1078	0	0
T93	3901	13	0	0
T96	3754	11	0	0
T101	3205	17	0	0
T102	13545	22	0	0
T122	11145	27	0	0
T123	19283	46	0	0
T156	2917	10	0	0
T157	5664	3	0	0
T158	9340	17	0	0
T159	1730	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1273	0	0
T93	3901	7	0	0
T96	3754	10	0	0
T101	3205	8	0	0
T102	13545	50	0	0
T122	11145	31	0	0
T123	19283	42	0	0
T135	28982	93	0	0
T156	2917	9	0	0
T157	5664	18	0	0
T158	9340	44	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1341	0	0
T93	3901	2	0	0
T96	3754	12	0	0
T101	3205	12	0	0
T102	13545	33	0	0
T122	11145	30	0	0
T123	19283	40	0	0
T135	28982	80	0	0
T156	2917	2	0	0
T157	5664	30	0	0
T158	9340	10	0	0