Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172276 |
1 |
|
|
T2 |
611 |
|
T6 |
558 |
|
T7 |
1494 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
85296 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
66772 |
1 |
|
|
T2 |
601 |
|
T6 |
550 |
|
T7 |
48 |
seven_bytes |
2975 |
1 |
|
|
T7 |
44 |
|
T18 |
26 |
|
T68 |
36 |
six_bytes |
2902 |
1 |
|
|
T7 |
41 |
|
T18 |
18 |
|
T68 |
45 |
five_bytes |
2892 |
1 |
|
|
T7 |
40 |
|
T18 |
21 |
|
T68 |
36 |
four_bytes |
2882 |
1 |
|
|
T7 |
32 |
|
T18 |
17 |
|
T68 |
34 |
three_bytes |
2837 |
1 |
|
|
T7 |
39 |
|
T18 |
33 |
|
T68 |
29 |
two_bytes |
2883 |
1 |
|
|
T7 |
39 |
|
T18 |
16 |
|
T68 |
36 |
one_byte |
2837 |
1 |
|
|
T7 |
35 |
|
T18 |
16 |
|
T68 |
35 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168864 |
1 |
|
|
T2 |
591 |
|
T6 |
542 |
|
T7 |
1474 |
auto[1] |
3412 |
1 |
|
|
T2 |
20 |
|
T6 |
16 |
|
T7 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172276 |
1 |
|
|
T2 |
611 |
|
T6 |
558 |
|
T7 |
1494 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172259 |
1 |
|
|
T2 |
611 |
|
T6 |
558 |
|
T7 |
1494 |
auto[1] |
17 |
1 |
|
|
T71 |
1 |
|
T170 |
1 |
|
T171 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1233 |
1 |
|
|
T2 |
10 |
|
T6 |
8 |
|
T7 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3412 |
1 |
|
|
T2 |
20 |
|
T6 |
16 |
|
T7 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163720 |
1 |
|
|
T2 |
1404 |
|
T6 |
563 |
|
T7 |
2680 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
77849 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
67255 |
1 |
|
|
T2 |
1383 |
|
T6 |
554 |
|
T7 |
78 |
seven_bytes |
2624 |
1 |
|
|
T7 |
61 |
|
T18 |
14 |
|
T68 |
44 |
six_bytes |
2720 |
1 |
|
|
T7 |
67 |
|
T18 |
15 |
|
T68 |
73 |
five_bytes |
2700 |
1 |
|
|
T7 |
84 |
|
T18 |
27 |
|
T68 |
70 |
four_bytes |
2598 |
1 |
|
|
T7 |
77 |
|
T18 |
21 |
|
T68 |
64 |
three_bytes |
2703 |
1 |
|
|
T7 |
81 |
|
T18 |
10 |
|
T68 |
61 |
two_bytes |
2584 |
1 |
|
|
T7 |
75 |
|
T18 |
19 |
|
T68 |
54 |
one_byte |
2687 |
1 |
|
|
T7 |
72 |
|
T18 |
26 |
|
T68 |
54 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160386 |
1 |
|
|
T2 |
1362 |
|
T6 |
545 |
|
T7 |
2654 |
auto[1] |
3334 |
1 |
|
|
T2 |
42 |
|
T6 |
18 |
|
T7 |
26 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163720 |
1 |
|
|
T2 |
1404 |
|
T6 |
563 |
|
T7 |
2680 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163711 |
1 |
|
|
T2 |
1404 |
|
T6 |
563 |
|
T7 |
2679 |
auto[1] |
9 |
1 |
|
|
T7 |
1 |
|
T31 |
1 |
|
T54 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1248 |
1 |
|
|
T2 |
21 |
|
T6 |
9 |
|
T7 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3334 |
1 |
|
|
T2 |
42 |
|
T6 |
18 |
|
T7 |
26 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
325450 |
1 |
|
|
T2 |
1316 |
|
T6 |
1037 |
|
T7 |
3930 |
auto[1] |
666 |
1 |
|
|
T8 |
7 |
|
T9 |
77 |
|
T10 |
90 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
161268 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
126473 |
1 |
|
|
T2 |
1295 |
|
T6 |
1022 |
|
T7 |
115 |
seven_bytes |
5637 |
1 |
|
|
T7 |
121 |
|
T18 |
33 |
|
T68 |
61 |
six_bytes |
5456 |
1 |
|
|
T7 |
98 |
|
T18 |
27 |
|
T68 |
73 |
five_bytes |
5687 |
1 |
|
|
T7 |
109 |
|
T18 |
36 |
|
T68 |
67 |
four_bytes |
5505 |
1 |
|
|
T7 |
92 |
|
T18 |
39 |
|
T68 |
81 |
three_bytes |
5329 |
1 |
|
|
T7 |
119 |
|
T18 |
35 |
|
T68 |
76 |
two_bytes |
5373 |
1 |
|
|
T7 |
106 |
|
T18 |
27 |
|
T68 |
80 |
one_byte |
5388 |
1 |
|
|
T7 |
105 |
|
T18 |
33 |
|
T68 |
60 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
319602 |
1 |
|
|
T2 |
1274 |
|
T6 |
1007 |
|
T7 |
3874 |
auto[1] |
6514 |
1 |
|
|
T2 |
42 |
|
T6 |
30 |
|
T7 |
56 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326116 |
1 |
|
|
T2 |
1316 |
|
T6 |
1037 |
|
T7 |
3930 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326091 |
1 |
|
|
T2 |
1316 |
|
T6 |
1037 |
|
T7 |
3930 |
auto[1] |
25 |
1 |
|
|
T14 |
1 |
|
T16 |
1 |
|
T9 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2295 |
1 |
|
|
T2 |
21 |
|
T6 |
15 |
|
T7 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6514 |
1 |
|
|
T2 |
42 |
|
T6 |
30 |
|
T7 |
56 |