Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

253762090

1

T1

1055

T2

39907

T3

32

full_word

179015673

1

T1

825

T2

61387

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	432777453	1			T1	1880		T2	101294		T3	40
auto[TlIntgErrCmd]	109	1			T124	5		T125	5		T126	7
auto[TlIntgErrData]	108	1			T124	5		T125	8		T126	6
auto[TlIntgErrBoth]	93	1			T125	7		T126	7		T177	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224161074

1

T1

1041

T2

68853

T3

1

auto[1]

208616689

1

T1

839

T2

32441

T3

39

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154964785	1			T1	1013		T2	25216		T3	1
auto[TlIntgErrNone]	partial	auto[1]	98797024	1			T1	42		T2	14691		T3	31
auto[TlIntgErrNone]	full_word	auto[0]	69196155	1			T1	28		T2	43637		T17	348
auto[TlIntgErrNone]	full_word	auto[1]	109819489	1			T1	797		T2	17750		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T125	2		T126	2		T177	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T124	5		T125	3		T126	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T178	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T177	1		T156	1		T179	2
auto[TlIntgErrData]	partial	auto[0]	38	1			T124	2		T125	2		T126	4
auto[TlIntgErrData]	partial	auto[1]	57	1			T124	3		T125	4		T126	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T125	1		T156	1		T180	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T125	1		T156	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T125	4		T126	1		T177	1
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T125	3		T126	5		T156	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T156	1		T174	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T126	1		T182	1		-	-