Unified Coverage Report :: Module :: kmac_app

Module : kmac_app

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.27	94.57	86.30		44.44	91.01	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_app_intf	83.27	94.57	86.30		44.44	91.01	100.00

---

Module Instance : tb.dut.u_app_intf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.27	94.57	86.30		44.44	91.01	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.87	94.07	88.60		44.44	92.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_appid_arb	95.05	87.50	92.68			100.00	100.00
u_prim_buf_state_err_check	100.00	100.00
u_prim_buf_state_kmac_sel	100.00	100.00
u_prim_buf_state_output_sel	100.00	100.00
u_prim_buf_state_output_valid	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_app

	Line No.	Total	Covered	Percent
TOTAL		221	209	94.57
ALWAYS	290	6	6	100.00
ALWAYS	304	0	0
ALWAYS	304	4	4	100.00
ALWAYS	329	6	6	100.00
ALWAYS	348	3	3	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
ALWAYS	376	3	3	100.00
ALWAYS	385	3	3	100.00
ALWAYS	388	1	0	0.00
ALWAYS	393	95	85	89.47
CONT_ASSIGN	653	1	1	100.00
ALWAYS	659	3	3	100.00
ALWAYS	682	18	18	100.00
ALWAYS	726	5	5	100.00
CONT_ASSIGN	746	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	768	1	1	100.00
ALWAYS	790	13	13	100.00
ALWAYS	815	6	6	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
ALWAYS	853	20	20	100.00
ALWAYS	904	8	7	87.50
ALWAYS	933	16	16	100.00
ALWAYS	960	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
290	2	2
291	2	2
292	2	2
			MISSING_ELSE
304	1	1
305	1	1
306	1	1
316	1	1
329	2	2
330	2	2
331	2	2
			MISSING_ELSE
348	1	1
349	1	1
350	1	1
372	1	1
373	1	1
376	2	2
377	1	1
385	3	3
388	0	1
393	1	1
395	1	1
398	1	1
399	1	1
402	1	1
405	1	1
408	1	1
409	1	1
411	1	1
413	1	1
414	1	1
417	1	1
418	1	1
420	1	1
422	1	1
423	1	1
426	1	1
427	1	1
428	1	1
430	1	1
432	1	1
437	1	1
444	1	1
446	1	1
450	1	1
453	1	1
458	1	1
459	1	1
460	1	1
461	1	1
463	1	1
466	1	1
471	1	1
473	1	1
474	1	1
476	1	1
481	1	1
482	1	1
486	1	1
488	1	1
489	1	1
491	1	1
493	1	1
498	1	1
500	1	1
501	1	1
503	1	1
504	1	1
506	1	1
511	1	1
515	1	1
516	1	1
517	1	1
522	1	1
525	1	1
532	1	1
536	1	1
542	1	1
543	1	1
550	1	1
553	1	1
558	0	1
564	0	1
567	0	1
568	0	1
576	1	1
579	1	1
580	1	1
			MISSING_ELSE
586	0	1
587	0	1
590	0	1
593	0	1
594	0	1
			==> MISSING_ELSE
599	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
607	1	1
608	0	1
			MISSING_ELSE
			MISSING_ELSE
615	1	1
616	1	1
617	1	1
618	1	1
623	1	1
624	1	1
625	1	1
626	1	1
627	1	1
639	1	1
640	1	1
			MISSING_ELSE
644	1	1
646	1	1
647	1	1
			MISSING_ELSE
			MISSING_ELSE
653	1	1
659	1	1
660	1	1
662	1	1
682	1	1
683	1	1
685	1	1
686	1	1
687	1	1
689	1	1
692	1	1
693	1	1
695	1	1
696	1	1
698	1	1
703	1	1
704	1	1
705	1	1
709	1	1
710	1	1
711	1	1
712	1	1
726	1	1
728	1	1
730	1	1
735	1	1
737	1	1
			MISSING_ELSE
746	1	1
757	1	1
768	1	1
790	1	1
791	1	1
792	1	1
794	1	1
795	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
			MISSING_ELSE
			MISSING_ELSE
815	1	1
816	1	1
817	1	1
820	1	1
823	1	1
825	1	1
			MISSING_ELSE
839	2	2
853	1	1
854	1	1
855	1	1
856	1	1
860	1	1
862	1	1
865	1	1
866	1	1
867	1	1
868	1	1
872	1	1
876	1	1
878	1	1
879	1	1
880	1	1
881	1	1
			MISSING_ELSE
885	1	1
886	1	1
888	1	1
891	1	1
			MISSING_ELSE
904	1	1
906	1	1
909	1	1
910	1	1
911	1	1
912	0	1
914	1	1
			MISSING_ELSE
921	1	1
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
939	1	1
940	1	1
941	1	1
942	1	1
943	1	1
944	1	1
946	1	1
947	1	1
948	1	1
949	1	1
950	1	1
			MISSING_ELSE
960	1	1
961	1	1
962	1	1

---

Cond Coverage for Module : kmac_app

	Total	Covered	Percent
Conditions	73	63	86.30
Logical	73	63	86.30
Non-Logical	0	0
Event	0	0

 LINE       305
 EXPRESSION (i == app_id)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (app_data_ready | fsm_data_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T6,T7

 LINE       306
 EXPRESSION (app_digest_done | fsm_digest_done_q)
             -------1-------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T6,T7

 LINE       306
 EXPRESSION (error_i | fsm_digest_done_q | sparse_fsm_error_o | service_rejected_error)
             ---1---   --------2--------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T8,T9,T10
0	0	1	0	Covered	T11,T12,T13
0	1	0	0	Covered	T1,T4,T5
1	0	0	0	Covered	T14,T15,T16

 LINE       427
 EXPRESSION (sw_cmd_i == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T6

 LINE       459
 EXPRESSION (app_i[app_id].valid && app_o[app_id].ready && app_i[app_id].last)
             ---------1---------    ---------2---------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T18
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T6,T7

 LINE       460
 EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T6,T7

 LINE       473
 EXPRESSION (kmac_valid_o && kmac_ready_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable	T6,T7,T18
1	1	Covered	T2,T6,T7

 LINE       503
 EXPRESSION (sw_cmd_i == CmdDone)
            ----------1----------

-1-	Status	Tests
0	Covered	T2,T17,T6
1	Covered	T2,T17,T6

 LINE       587
 EXPRESSION (app_i[app_id].valid && app_i[app_id].last)
             ---------1---------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       644
 EXPRESSION (st_d != StTerminalError)
            ------------1------------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T1,T2,T3

 LINE       646
 EXPRESSION (keymgr_key_used && ((!keymgr_key_i.valid)))
             -------1-------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T19
1	1	Covered	T1,T4,T5

 LINE       653
 EXPRESSION (((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid})) ? 1'b1 : ((st_d == StIdle) ? 1'b0 : err_during_sw_q))
             -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       653
 SUB-EXPRESSION ((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}))
                 ---------1--------    -----------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T2,T17,T6
1	1	Not Covered

 LINE       653
 SUB-EXPRESSION (mux_sel == SelSw)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T6

 LINE       653
 SUB-EXPRESSION ((st_d == StIdle) ? 1'b0 : err_during_sw_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       653
 SUB-EXPRESSION (st_d == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

 LINE       728
 EXPRESSION ((mux_sel_buf_err_check != SelSw) && sw_valid_i)
             ----------------1---------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T12,T13

 LINE       728
 SUB-EXPRESSION (mux_sel_buf_err_check != SelSw)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T2,T17,T6
1	Covered	T1,T2,T3

 LINE       735
 EXPRESSION (app_active_o && (sw_cmd_i != CmdNone))
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T20,T21,T22

 LINE       735
 SUB-EXPRESSION (sw_cmd_i != CmdNone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T6

 LINE       865
 EXPRESSION (kmac_pkg::AppCfg[app_id].Mode == AppKMAC)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T6

 LINE       872
 EXPRESSION (keymgr_key_used && keymgr_key_i.valid)
             -------1-------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T15,T21,T23
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T6,T7

 LINE       910
 EXPRESSION (app_id == i)
            ------1------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T6

 LINE       911
 EXPRESSION (kmac_pkg::AppCfg[i].PrefixMode == 1'b0)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Not Covered

 LINE       943
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T6

 LINE       943
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T6

 LINE       944
 EXPRESSION ((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3) ? Sha3 : CShake)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Not Covered

 LINE       944
 SUB-EXPRESSION (kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Not Covered

 LINE       947
 EXPRESSION (st == StIdle)
            -------1------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

---

FSM Coverage for Module : kmac_app

Summary for FSM :: st

	Total	Covered	Percent
States	14	13	92.86	(Not included in score)
Transitions	45	20	44.44
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAppCfg	423	Covered	T1,T2,T6
StAppMsg	450	Covered	T2,T6,T7
StAppOutLen	461	Covered	T2,T6,T7
StAppProcess	463	Covered	T2,T6,T7
StAppWait	482	Covered	T2,T6,T7
StError	444	Covered	T1,T4,T5
StErrorAwaitApp	558	Not Covered
StErrorAwaitSw	553	Covered	T1,T4,T5
StErrorServiceRejected	550	Covered	T8,T9,T10
StErrorWaitAbsorbed	568	Covered	T1,T4,T5
StIdle	432	Covered	T1,T2,T3
StKeyMgrErrKeyNotValid	647	Covered	T1,T4,T5
StSw	428	Covered	T2,T17,T6
StTerminalError	640	Covered	T11,T12,T13

transitions	Line No.	Covered	Tests
StAppCfg->StAppMsg	450	Covered	T2,T6,T7
StAppCfg->StError	444	Covered	T8,T9,T10
StAppCfg->StKeyMgrErrKeyNotValid	647	Covered	T1,T4,T5
StAppCfg->StTerminalError	640	Not Covered
StAppMsg->StAppOutLen	461	Covered	T2,T6,T7
StAppMsg->StAppProcess	463	Covered	T2,T6,T7
StAppMsg->StKeyMgrErrKeyNotValid	647	Not Covered
StAppMsg->StTerminalError	640	Covered	T24,T25,T26
StAppOutLen->StAppProcess	474	Covered	T2,T6,T7
StAppOutLen->StKeyMgrErrKeyNotValid	647	Not Covered
StAppOutLen->StTerminalError	640	Not Covered
StAppProcess->StAppWait	482	Covered	T2,T6,T7
StAppProcess->StKeyMgrErrKeyNotValid	647	Not Covered
StAppProcess->StTerminalError	640	Not Covered
StAppWait->StIdle	488	Covered	T2,T6,T7
StAppWait->StKeyMgrErrKeyNotValid	647	Not Covered
StAppWait->StTerminalError	640	Not Covered
StError->StErrorAwaitApp	558	Not Covered
StError->StErrorAwaitSw	553	Covered	T1,T4,T5
StError->StErrorServiceRejected	550	Covered	T8,T9,T10
StError->StErrorWaitAbsorbed	568	Not Covered
StError->StKeyMgrErrKeyNotValid	647	Not Covered
StError->StTerminalError	640	Not Covered
StErrorAwaitApp->StErrorWaitAbsorbed	594	Not Covered
StErrorAwaitApp->StKeyMgrErrKeyNotValid	647	Not Covered
StErrorAwaitApp->StTerminalError	640	Not Covered
StErrorAwaitSw->StErrorWaitAbsorbed	580	Covered	T1,T4,T5
StErrorAwaitSw->StKeyMgrErrKeyNotValid	647	Not Covered
StErrorAwaitSw->StTerminalError	640	Not Covered
StErrorServiceRejected->StIdle	618	Covered	T8,T9,T10
StErrorServiceRejected->StKeyMgrErrKeyNotValid	647	Not Covered
StErrorServiceRejected->StTerminalError	640	Not Covered
StErrorWaitAbsorbed->StIdle	605	Covered	T1,T4,T5
StErrorWaitAbsorbed->StKeyMgrErrKeyNotValid	647	Not Covered
StErrorWaitAbsorbed->StTerminalError	640	Not Covered
StIdle->StAppCfg	423	Covered	T1,T2,T6
StIdle->StKeyMgrErrKeyNotValid	647	Not Covered
StIdle->StSw	428	Covered	T2,T17,T6
StIdle->StTerminalError	640	Covered	T27,T28,T29
StKeyMgrErrKeyNotValid->StError	511	Covered	T1,T4,T5
StKeyMgrErrKeyNotValid->StTerminalError	640	Not Covered
StSw->StIdle	504	Covered	T2,T17,T6
StSw->StKeyMgrErrKeyNotValid	647	Not Covered
StSw->StTerminalError	640	Covered	T11,T12,T13
StTerminalError->StKeyMgrErrKeyNotValid	647	Not Covered

---

Branch Coverage for Module : kmac_app

	Line No.	Total	Covered	Percent
Branches		89	81	91.01
TERNARY	653	3	2	66.67
IF	290	4	4	100.00
IF	305	2	2	100.00
IF	329	4	4	100.00
IF	376	2	2	100.00
IF	385	2	2	100.00
CASE	420	32	26	81.25
IF	639	2	2	100.00
IF	644	3	3	100.00
IF	659	2	2	100.00
CASE	689	4	4	100.00
IF	728	3	3	100.00
IF	792	3	3	100.00
IF	817	2	2	100.00
CASE	862	7	7	100.00
CASE	906	3	3	100.00
IF	933	8	7	87.50
CASE	960	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_app.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	653	(((mux_sel == SelSw) && (st_d inside {StError, StKeyMgrErrKeyNotValid}))) ? 
-2-:	653	((st_d == StIdle)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	290	if ((!rst_ni))
-2-:	291	if (service_rejected_error_set)
-3-:	292	if (service_rejected_error_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((i == app_id))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if ((!rst_ni))
-2-:	330	if (clr_appid)
-3-:	331	if (set_appid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	376	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	385	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	case (st)
-2-:	422	if (arb_valid)
-3-:	427	if ((sw_cmd_i == CmdStart))
-4-:	437	if (((kmac_pkg::AppCfg[app_id].Mode == AppKMAC) && prim_mubi_pkg::mubi4_test_false_strict(entropy_ready_i)))
-5-:	459	if (((app_i[app_id].valid && app_o[app_id].ready) && app_i[app_id].last))
-6-:	460	if ((kmac_pkg::AppCfg[app_id].Mode == AppKMAC))
-7-:	473	if ((kmac_valid_o && kmac_ready_i))
-8-:	486	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i))
-9-:	503	if ((sw_cmd_i == CmdDone))
-10-:	532	case ({err_processed_i, ((app_i[app_id].valid && app_i[app_id].last) || err_during_sw_q)})
-11-:	543	if (service_rejected_error)
-12-:	576	if (err_processed_i)
-13-:	587	if ((app_i[app_id].valid && app_i[app_id].last))
-14-:	599	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_i))
-15-:	607	if (err_during_sw_q)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T6
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAppCfg	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
StAppCfg	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
StAppMsg	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppMsg	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppMsg	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppOutLen	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppOutLen	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T18
StAppProcess	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T6,T7
StAppWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T6,T7
StSw	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T17,T6
StSw	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T17,T6
StKeyMgrErrKeyNotValid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StError	-	-	-	-	-	-	-	-	2'b00	-	-	-	-	-	Covered	T1,T4,T5
StError	-	-	-	-	-	-	-	-	2'b01	1	-	-	-	-	Covered	T8,T9,T10
StError	-	-	-	-	-	-	-	-	2'b01	0	-	-	-	-	Covered	T1,T4,T5
StError	-	-	-	-	-	-	-	-	2'b10	-	-	-	-	-	Not Covered
StError	-	-	-	-	-	-	-	-	2'b11	-	-	-	-	-	Not Covered
StError	-	-	-	-	-	-	-	-	default	-	-	-	-	-	Not Covered
StErrorAwaitSw	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T4,T5
StErrorAwaitSw	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T4,T5
StErrorAwaitApp	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StErrorAwaitApp	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StErrorWaitAbsorbed	-	-	-	-	-	-	-	-	-	-	-	-	1	1	Not Covered
StErrorWaitAbsorbed	-	-	-	-	-	-	-	-	-	-	-	-	1	0	Covered	T1,T4,T5
StErrorWaitAbsorbed	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T4,T5
StErrorServiceRejected	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T28,T29

	LineNo.	Expression
-1-:	639	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	644	if ((st_d != StTerminalError))
-2-:	646	if ((keymgr_key_used && (!keymgr_key_i.valid)))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
0	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	659	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	case (mux_sel_buf_kmac)

Branches:

-1-	Status	Tests
SelApp	Covered	T2,T6,T7
SelOutLen	Covered	T2,T6,T7
SelSw	Covered	T2,T17,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	728	if (((mux_sel_buf_err_check != SelSw) && sw_valid_i))
-2-:	735	if ((app_active_o && (sw_cmd_i != CmdNone)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T12,T13
0	1	Covered	T20,T21,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (((mux_sel_buf_output == SelSw) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))
-2-:	798	if (keymgr_key_en_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T6,T19
1	0	Covered	T2,T17,T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	817	if ((((st == StAppWait) && prim_mubi_pkg::mubi4_test_true_strict(absorbed_i)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	case (st)
-2-:	876	if (keymgr_key_en_i)
-3-:	885	if (kmac_en_o)
-4-:	886	if ((!keymgr_key_en_i))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	-	-	-	Covered	T1,T2,T6
StSw	1	-	-	Covered	T2,T6,T19
StSw	0	-	-	Covered	T2,T17,T6
StSw	-	1	1	Covered	T2,T17,T6
StSw	-	1	0	Covered	T2,T6,T19
StSw	-	0	-	Covered	T2,T6,T19
default	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	906	case (st)

Branches:

-1-	Status	Tests
StAppCfg StAppMsg StAppOutLen StAppProcess StAppWait	Covered	T1,T2,T6
StSw	Covered	T2,T17,T6
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	933	if ((!rst_ni))
-2-:	937	if (clr_appid)
-3-:	942	if (set_appid)
-4-:	943	((kmac_pkg::AppCfg[arb_idx].Mode == AppKMAC)) ? 
-5-:	944	((kmac_pkg::AppCfg[arb_idx].Mode == AppSHA3)) ? 
-6-:	947	if ((st == StIdle))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T6
0	0	1	1	-	-	Covered	T1,T2,T6
0	0	1	0	-	-	Covered	T2,T6,T7
0	0	1	-	1	-	Not Covered
0	0	1	-	0	-	Covered	T1,T2,T6
0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	-	-	0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	960	case ({fsm_err.valid, mux_err.valid})

Branches:

-1-	Status	Tests
2'bz1	Covered	T11,T12,T13
2'b10	Covered	T1,T4,T5
default	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_app

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	1	1	100.00	1	100.00
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AppIntfInRange_A	1018	1018	0	0
SideloadKeySameToDigest_A	1018	1018	0	0
u_state_regs_A	2147483647	2147483647	0	0

AppIntfInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T30	1	1	0	0

SideloadKeySameToDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T19	1	1	0	0
T30	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	150167	150100	0	0
T2	113408	113403	0	0
T3	1580	1525	0	0
T4	138096	138014	0	0
T5	192450	192390	0	0
T6	284271	284177	0	0
T7	604144	604066	0	0
T17	13035	12938	0	0
T19	652851	652794	0	0
T30	1109	1016	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
AppIntfUseDifferentSizeKey_C	2147483647	2793	0

AppIntfUseDifferentSizeKey_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2793	0
T1	150167	14	0
T2	113408	19	0
T3	1580	0	0
T4	138096	14	0
T5	192450	13	0
T6	284271	8	0
T7	604144	15	0
T14	0	8	0
T17	13035	0	0
T19	652851	0	0
T30	1109	0	0
T31	0	9	0
T32	0	3	0
T33	0	1	0