Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	242017	0	0
entropy_period_rd_A	2147483647	1439	0	0
intr_enable_rd_A	2147483647	2198	0	0
prefix_0_rd_A	2147483647	1467	0	0
prefix_10_rd_A	2147483647	1435	0	0
prefix_1_rd_A	2147483647	1534	0	0
prefix_2_rd_A	2147483647	1368	0	0
prefix_3_rd_A	2147483647	1448	0	0
prefix_4_rd_A	2147483647	1393	0	0
prefix_5_rd_A	2147483647	1528	0	0
prefix_6_rd_A	2147483647	1514	0	0
prefix_7_rd_A	2147483647	1543	0	0
prefix_8_rd_A	2147483647	1582	0	0
prefix_9_rd_A	2147483647	1536	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	242017	0	0
T13	2842	0	0	0
T15	557795	82192	0	0
T42	0	23537	0	0
T43	0	21361	0	0
T113	174140	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	2	0	0
T131	0	112041	0	0
T132	0	5	0	0
T133	0	2	0	0
T134	0	232	0	0
T136	621239	0	0	0
T137	310430	0	0	0
T138	178161	0	0	0
T139	149652	0	0	0
T140	15792	0	0	0
T141	709549	0	0	0
T142	779	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1439	0	0
T124	15047	65	0	0
T125	25497	81	0	0
T126	23068	157	0	0
T130	3025	2	0	0
T135	4372	14	0	0
T153	72422	111	0	0
T154	1617	3	0	0
T155	2779	14	0	0
T156	24663	131	0	0
T157	5007	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2198	0	0
T124	15047	75	0	0
T125	25497	91	0	0
T126	23068	133	0	0
T130	3025	11	0	0
T135	4372	6	0	0
T153	72422	253	0	0
T154	1617	1	0	0
T155	2779	14	0	0
T156	24663	186	0	0
T158	971	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T124	15047	21	0	0
T125	25497	49	0	0
T126	23068	69	0	0
T130	3025	7	0	0
T135	4372	8	0	0
T153	72422	228	0	0
T154	1617	2	0	0
T155	2779	12	0	0
T156	24663	77	0	0
T157	5007	12	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1435	0	0
T124	15047	54	0	0
T125	25497	25	0	0
T126	23068	85	0	0
T130	3025	7	0	0
T135	4372	5	0	0
T153	72422	203	0	0
T154	1617	2	0	0
T155	2779	8	0	0
T156	24663	87	0	0
T157	5007	4	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534	0	0
T124	15047	34	0	0
T125	25497	59	0	0
T126	23068	82	0	0
T130	3025	6	0	0
T135	4372	11	0	0
T153	72422	202	0	0
T154	1617	2	0	0
T155	2779	7	0	0
T156	24663	87	0	0
T157	5007	4	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1368	0	0
T124	15047	44	0	0
T125	25497	27	0	0
T126	23068	93	0	0
T130	3025	6	0	0
T135	4372	9	0	0
T153	72422	210	0	0
T154	1617	6	0	0
T155	2779	10	0	0
T156	24663	69	0	0
T157	5007	8	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1448	0	0
T124	15047	30	0	0
T125	25497	57	0	0
T126	23068	84	0	0
T130	3025	8	0	0
T135	4372	16	0	0
T153	72422	199	0	0
T154	1617	3	0	0
T155	2779	11	0	0
T156	24663	92	0	0
T157	5007	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393	0	0
T124	15047	39	0	0
T125	25497	19	0	0
T126	23068	75	0	0
T130	3025	7	0	0
T135	4372	6	0	0
T153	72422	198	0	0
T154	1617	6	0	0
T155	2779	3	0	0
T156	24663	109	0	0
T157	5007	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1528	0	0
T124	15047	53	0	0
T125	25497	17	0	0
T126	23068	68	0	0
T130	3025	2	0	0
T135	4372	10	0	0
T153	72422	189	0	0
T154	1617	2	0	0
T155	2779	12	0	0
T156	24663	85	0	0
T157	5007	8	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1514	0	0
T124	15047	40	0	0
T125	25497	39	0	0
T126	23068	94	0	0
T130	3025	3	0	0
T135	4372	16	0	0
T153	72422	194	0	0
T155	2779	1	0	0
T156	24663	88	0	0
T157	5007	6	0	0
T159	72346	225	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T124	15047	53	0	0
T125	25497	43	0	0
T126	23068	86	0	0
T135	4372	1	0	0
T153	72422	217	0	0
T154	1617	3	0	0
T155	2779	17	0	0
T156	24663	85	0	0
T157	5007	10	0	0
T159	72346	224	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T124	15047	34	0	0
T125	25497	50	0	0
T126	23068	57	0	0
T130	3025	12	0	0
T135	4372	7	0	0
T153	72422	251	0	0
T155	2779	10	0	0
T156	24663	118	0	0
T157	5007	4	0	0
T159	72346	235	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1536	0	0
T124	15047	31	0	0
T125	25497	36	0	0
T126	23068	63	0	0
T130	3025	6	0	0
T135	4372	8	0	0
T153	72422	258	0	0
T155	2779	10	0	0
T156	24663	87	0	0
T157	5007	7	0	0
T159	72346	255	0	0