Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260244189

1

T1

13588

T2

62206

T3

3587

full_word

184169069

1

T1

109578

T2

326317

T3

3306

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444413008	1			T1	123166		T2	388523		T3	6893
auto[TlIntgErrCmd]	69	1			T134	5		T135	5		T136	3
auto[TlIntgErrData]	93	1			T134	1		T135	5		T136	2
auto[TlIntgErrBoth]	88	1			T134	4		T135	10		T136	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229637306

1

T1

33376

T2

121946

T3

4453

auto[1]

214775952

1

T1

89790

T2

266577

T3

2440

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158353979	1			T1	12238		T2	58365		T3	2430
auto[TlIntgErrNone]	partial	auto[1]	101889979	1			T1	1350		T2	3841		T3	1157
auto[TlIntgErrNone]	full_word	auto[0]	71283210	1			T1	21138		T2	63581		T3	2023
auto[TlIntgErrNone]	full_word	auto[1]	112885840	1			T1	88440		T2	262736		T3	1283
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T134	1		T135	2		T136	1
auto[TlIntgErrCmd]	partial	auto[1]	37	1			T134	2		T135	3		T136	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T134	2		T190	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T191	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	44	1			T134	1		T135	2		T155	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T135	3		T136	2		T155	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T177	1		T192	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T194	2		T190	1		T195	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T134	3		T135	3		T136	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T135	7		T136	2		T155	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T134	1		T196	1		T193	2