Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	433378	0	0
entropy_period_rd_A	2147483647	1100	0	0
intr_enable_rd_A	2147483647	1610	0	0
prefix_0_rd_A	2147483647	812	0	0
prefix_10_rd_A	2147483647	854	0	0
prefix_1_rd_A	2147483647	865	0	0
prefix_2_rd_A	2147483647	879	0	0
prefix_3_rd_A	2147483647	796	0	0
prefix_4_rd_A	2147483647	916	0	0
prefix_5_rd_A	2147483647	901	0	0
prefix_6_rd_A	2147483647	845	0	0
prefix_7_rd_A	2147483647	820	0	0
prefix_8_rd_A	2147483647	858	0	0
prefix_9_rd_A	2147483647	891	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	433378	0	0
T52	575405	87113	0	0
T53	0	42600	0	0
T54	0	86470	0	0
T134	0	2	0	0
T135	0	3	0	0
T140	0	62867	0	0
T141	0	64444	0	0
T142	0	86989	0	0
T143	0	22	0	0
T144	0	1	0	0
T146	14613	0	0	0
T147	1914	0	0	0
T148	632881	0	0	0
T149	7121	0	0	0
T150	1950	0	0	0
T151	626113	0	0	0
T152	204617	0	0	0
T153	409989	0	0	0
T154	192503	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1100	0	0
T90	7150	40	0	0
T94	2466	2	0	0
T104	4357	12	0	0
T165	3838	3	0	0
T166	4345	10	0	0
T167	2071	9	0	0
T168	14439	3	0	0
T169	1733	16	0	0
T170	4936	6	0	0
T171	3482	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T90	7150	35	0	0
T94	2466	5	0	0
T137	1130	15	0	0
T165	3838	5	0	0
T166	4345	16	0	0
T167	2071	20	0	0
T169	1733	15	0	0
T172	1682	1	0	0
T173	1602	20	0	0
T174	1501	5	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	812	0	0
T90	7150	16	0	0
T94	2466	2	0	0
T97	5897	31	0	0
T104	4357	2	0	0
T165	3838	5	0	0
T166	4345	1	0	0
T167	2071	1	0	0
T171	3482	4	0	0
T175	11864	41	0	0
T176	1889	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	854	0	0
T90	7150	27	0	0
T97	5897	31	0	0
T104	4357	22	0	0
T165	3838	9	0	0
T166	4345	3	0	0
T167	2071	8	0	0
T169	1733	4	0	0
T170	4936	12	0	0
T171	3482	13	0	0
T175	11864	44	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	865	0	0
T90	7150	32	0	0
T97	5897	33	0	0
T104	4357	13	0	0
T165	3838	1	0	0
T167	2071	8	0	0
T169	1733	2	0	0
T170	4936	11	0	0
T171	3482	7	0	0
T175	11864	71	0	0
T176	1889	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	879	0	0
T90	7150	41	0	0
T94	2466	6	0	0
T97	5897	25	0	0
T104	4357	12	0	0
T165	3838	2	0	0
T166	4345	1	0	0
T167	2071	3	0	0
T170	4936	6	0	0
T171	3482	12	0	0
T175	11864	45	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	796	0	0
T90	7150	24	0	0
T94	2466	5	0	0
T97	5897	24	0	0
T104	4357	19	0	0
T165	3838	9	0	0
T166	4345	7	0	0
T167	2071	1	0	0
T170	4936	8	0	0
T171	3482	6	0	0
T175	11864	30	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	916	0	0
T90	7150	27	0	0
T97	5897	31	0	0
T104	4357	17	0	0
T165	3838	13	0	0
T169	1733	2	0	0
T170	4936	8	0	0
T171	3482	2	0	0
T175	11864	76	0	0
T176	1889	9	0	0
T177	10698	11	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	901	0	0
T90	7150	26	0	0
T97	5897	23	0	0
T104	4357	17	0	0
T165	3838	2	0	0
T166	4345	6	0	0
T169	1733	4	0	0
T170	4936	9	0	0
T171	3482	12	0	0
T175	11864	12	0	0
T176	1889	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	845	0	0
T90	7150	24	0	0
T94	2466	8	0	0
T97	5897	22	0	0
T104	4357	17	0	0
T165	3838	10	0	0
T166	4345	4	0	0
T167	2071	3	0	0
T169	1733	3	0	0
T170	4936	3	0	0
T171	3482	15	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	820	0	0
T90	7150	32	0	0
T94	2466	14	0	0
T97	5897	28	0	0
T104	4357	21	0	0
T165	3838	4	0	0
T166	4345	4	0	0
T167	2071	7	0	0
T169	1733	8	0	0
T170	4936	10	0	0
T171	3482	4	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	858	0	0
T90	7150	30	0	0
T94	2466	2	0	0
T97	5897	24	0	0
T104	4357	10	0	0
T165	3838	8	0	0
T166	4345	4	0	0
T167	2071	5	0	0
T169	1733	2	0	0
T170	4936	7	0	0
T171	3482	10	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	891	0	0
T90	7150	25	0	0
T94	2466	2	0	0
T97	5897	24	0	0
T104	4357	9	0	0
T165	3838	9	0	0
T166	4345	6	0	0
T167	2071	1	0	0
T170	4936	14	0	0
T171	3482	5	0	0
T175	11864	37	0	0