Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177633 |
1 |
|
|
T7 |
413 |
|
T8 |
1899 |
|
T9 |
91 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90850 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65432 |
1 |
|
|
T7 |
404 |
|
T8 |
1060 |
|
T9 |
89 |
seven_bytes |
3002 |
1 |
|
|
T8 |
15 |
|
T21 |
42 |
|
T22 |
27 |
six_bytes |
3025 |
1 |
|
|
T8 |
26 |
|
T21 |
42 |
|
T22 |
47 |
five_bytes |
3108 |
1 |
|
|
T8 |
11 |
|
T21 |
38 |
|
T22 |
42 |
four_bytes |
3187 |
1 |
|
|
T8 |
26 |
|
T21 |
36 |
|
T22 |
30 |
three_bytes |
3027 |
1 |
|
|
T8 |
26 |
|
T21 |
41 |
|
T22 |
29 |
two_bytes |
2997 |
1 |
|
|
T8 |
15 |
|
T21 |
33 |
|
T22 |
33 |
one_byte |
3005 |
1 |
|
|
T8 |
18 |
|
T21 |
41 |
|
T22 |
40 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174107 |
1 |
|
|
T7 |
395 |
|
T8 |
1855 |
|
T9 |
87 |
auto[1] |
3526 |
1 |
|
|
T7 |
18 |
|
T8 |
44 |
|
T9 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177633 |
1 |
|
|
T7 |
413 |
|
T8 |
1899 |
|
T9 |
91 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177619 |
1 |
|
|
T7 |
412 |
|
T8 |
1899 |
|
T9 |
91 |
auto[1] |
14 |
1 |
|
|
T7 |
1 |
|
T10 |
1 |
|
T176 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1238 |
1 |
|
|
T7 |
9 |
|
T8 |
15 |
|
T9 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3526 |
1 |
|
|
T7 |
18 |
|
T8 |
44 |
|
T9 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184887 |
1 |
|
|
T7 |
286 |
|
T8 |
1472 |
|
T9 |
76 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92305 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
70686 |
1 |
|
|
T7 |
281 |
|
T8 |
446 |
|
T9 |
75 |
seven_bytes |
3122 |
1 |
|
|
T8 |
25 |
|
T21 |
22 |
|
T22 |
23 |
six_bytes |
3126 |
1 |
|
|
T8 |
25 |
|
T21 |
24 |
|
T22 |
18 |
five_bytes |
3166 |
1 |
|
|
T8 |
32 |
|
T21 |
21 |
|
T22 |
30 |
four_bytes |
3164 |
1 |
|
|
T8 |
34 |
|
T21 |
26 |
|
T22 |
33 |
three_bytes |
3045 |
1 |
|
|
T8 |
27 |
|
T21 |
16 |
|
T22 |
28 |
two_bytes |
3192 |
1 |
|
|
T8 |
30 |
|
T21 |
20 |
|
T22 |
23 |
one_byte |
3081 |
1 |
|
|
T8 |
24 |
|
T21 |
24 |
|
T22 |
29 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
181290 |
1 |
|
|
T7 |
276 |
|
T8 |
1442 |
|
T9 |
74 |
auto[1] |
3597 |
1 |
|
|
T7 |
10 |
|
T8 |
30 |
|
T9 |
2 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184887 |
1 |
|
|
T7 |
286 |
|
T8 |
1472 |
|
T9 |
76 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
184877 |
1 |
|
|
T7 |
286 |
|
T8 |
1472 |
|
T9 |
76 |
auto[1] |
10 |
1 |
|
|
T49 |
1 |
|
T177 |
1 |
|
T11 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1279 |
1 |
|
|
T7 |
5 |
|
T8 |
9 |
|
T9 |
1 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3597 |
1 |
|
|
T7 |
10 |
|
T8 |
30 |
|
T9 |
2 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359040 |
1 |
|
|
T2 |
2 |
|
T7 |
900 |
|
T8 |
4264 |
auto[1] |
688 |
1 |
|
|
T10 |
72 |
|
T11 |
75 |
|
T12 |
72 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
182911 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
133302 |
1 |
|
|
T2 |
2 |
|
T7 |
888 |
|
T8 |
1138 |
seven_bytes |
6230 |
1 |
|
|
T8 |
93 |
|
T21 |
31 |
|
T22 |
161 |
six_bytes |
6181 |
1 |
|
|
T8 |
66 |
|
T21 |
40 |
|
T22 |
154 |
five_bytes |
6474 |
1 |
|
|
T8 |
106 |
|
T21 |
26 |
|
T22 |
162 |
four_bytes |
6054 |
1 |
|
|
T8 |
85 |
|
T21 |
38 |
|
T22 |
148 |
three_bytes |
6339 |
1 |
|
|
T8 |
78 |
|
T21 |
40 |
|
T22 |
154 |
two_bytes |
6054 |
1 |
|
|
T8 |
81 |
|
T21 |
25 |
|
T22 |
167 |
one_byte |
6183 |
1 |
|
|
T8 |
86 |
|
T21 |
30 |
|
T22 |
131 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
352735 |
1 |
|
|
T2 |
2 |
|
T7 |
876 |
|
T8 |
4194 |
auto[1] |
6993 |
1 |
|
|
T7 |
24 |
|
T8 |
70 |
|
T9 |
6 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359728 |
1 |
|
|
T2 |
2 |
|
T7 |
900 |
|
T8 |
4264 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
359699 |
1 |
|
|
T2 |
2 |
|
T7 |
899 |
|
T8 |
4264 |
auto[1] |
29 |
1 |
|
|
T7 |
1 |
|
T15 |
1 |
|
T79 |
2 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2424 |
1 |
|
|
T7 |
12 |
|
T8 |
21 |
|
T9 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6993 |
1 |
|
|
T7 |
24 |
|
T8 |
70 |
|
T9 |
6 |