Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261486487	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185910528

1

T1

190901

T2

151

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	232121982	1			T1	251541		T2	74		T3	1
values[0x0]	103480014	1			T1	106893		T2	49		T3	12
values[0x1]	111795019	1			T1	114973		T2	42		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203231970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

244165045

1

T1

253199

T2

153

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1980462	1			T1	224		T17	1073		T18	3362
valid_sources[0x01]	1502991	1			T1	177		T17	1185		T18	3670
valid_sources[0x02]	1328409	1			T1	188		T17	1026		T18	3241
valid_sources[0x03]	1327565	1			T1	189		T17	1118		T18	3237
valid_sources[0x04]	3645400	1			T1	173		T17	1129		T18	3154
valid_sources[0x05]	1329395	1			T1	177		T3	2		T17	1088
valid_sources[0x06]	1334948	1			T1	187		T17	1188		T18	3456
valid_sources[0x07]	1328115	1			T1	164		T17	1098		T18	3832
valid_sources[0x08]	1856775	1			T1	212		T17	1107		T18	3682
valid_sources[0x09]	1354712	1			T1	192		T17	1116		T18	3241
valid_sources[0x0a]	1566453	1			T1	174		T17	1150		T18	3445
valid_sources[0x0b]	1797552	1			T1	199		T17	1065		T18	3444
valid_sources[0x0c]	1324929	1			T1	175		T17	1159		T18	3428
valid_sources[0x0d]	1327096	1			T1	176		T17	1009		T18	3631
valid_sources[0x0e]	2158615	1			T1	190		T17	1039		T18	3608
valid_sources[0x0f]	1324150	1			T1	200		T17	1154		T18	3740
valid_sources[0x10]	1325143	1			T1	190		T17	983		T18	3744
valid_sources[0x11]	1972078	1			T1	195		T17	1148		T18	3260
valid_sources[0x12]	1332082	1			T1	180		T17	1111		T18	3092
valid_sources[0x13]	1330851	1			T1	222		T17	1171		T18	3769
valid_sources[0x14]	1331438	1			T1	197		T17	1226		T18	3662
valid_sources[0x15]	1334828	1			T1	206		T17	1021		T18	3473
valid_sources[0x16]	1469304	1			T1	197		T17	1078		T18	3452
valid_sources[0x17]	1333149	1			T1	185		T17	1081		T18	3423
valid_sources[0x18]	2258466	1			T1	191		T17	1153		T18	3886
valid_sources[0x19]	1358242	1			T1	215		T17	1138		T18	3752
valid_sources[0x1a]	1987968	1			T1	205		T17	1273		T18	3760
valid_sources[0x1b]	1328236	1			T1	168		T17	1048		T18	3267
valid_sources[0x1c]	1324606	1			T1	180		T17	1143		T18	3454
valid_sources[0x1d]	1334056	1			T1	181		T17	1211		T18	3742
valid_sources[0x1e]	1333700	1			T1	210		T17	1240		T18	3368
valid_sources[0x1f]	2414986	1			T1	188		T17	1095		T18	3551
valid_sources[0x20]	1326454	1			T1	186		T17	1198		T18	2993
valid_sources[0x21]	1396493	1			T1	208		T17	1121		T18	4037
valid_sources[0x22]	1537883	1			T1	196		T17	1034		T18	3617
valid_sources[0x23]	3962603	1			T1	194		T17	1050		T18	3542
valid_sources[0x24]	1325590	1			T1	180		T17	1127		T18	3563
valid_sources[0x25]	1334384	1			T1	189		T17	1186		T18	3579
valid_sources[0x26]	1350966	1			T1	193		T17	1081		T18	3750
valid_sources[0x27]	1330619	1			T1	192		T17	1081		T18	3725
valid_sources[0x28]	2219136	1			T1	193		T17	1107		T18	3889
valid_sources[0x29]	1555026	1			T1	193		T17	1116		T18	3482
valid_sources[0x2a]	1331769	1			T1	184		T17	1212		T18	3061
valid_sources[0x2b]	1466139	1			T1	190		T17	1096		T18	3511
valid_sources[0x2c]	3543861	1			T1	177		T17	1034		T18	3740
valid_sources[0x2d]	1334267	1			T1	189		T3	9		T17	1161
valid_sources[0x2e]	1326012	1			T1	177		T17	1159		T18	3520
valid_sources[0x2f]	3747353	1			T1	186		T17	1125		T18	3427
valid_sources[0x30]	1978029	1			T1	203		T17	1153		T18	3524
valid_sources[0x31]	3947243	1			T1	208		T17	1158		T18	3393
valid_sources[0x32]	1324970	1			T1	171		T17	1164		T18	3578
valid_sources[0x33]	1973854	1			T1	171		T17	1115		T18	3363
valid_sources[0x34]	1492421	1			T1	178		T17	1028		T18	3315
valid_sources[0x35]	1324844	1			T1	182		T17	1053		T18	3846
valid_sources[0x36]	1466709	1			T1	177		T17	1057		T18	3626
valid_sources[0x37]	1335299	1			T1	175		T17	1187		T18	3638
valid_sources[0x38]	1325866	1			T1	195		T17	1142		T18	3514
valid_sources[0x39]	1972755	1			T1	185		T17	1130		T18	3382
valid_sources[0x3a]	3670012	1			T1	192		T17	1150		T18	3697
valid_sources[0x3b]	1341810	1			T1	181		T17	1145		T18	3607
valid_sources[0x3c]	1444587	1			T1	189		T17	1050		T18	3601
valid_sources[0x3d]	1337184	1			T1	166		T17	1081		T18	3492
valid_sources[0x3e]	1390676	1			T1	190		T17	1079		T18	3455
valid_sources[0x3f]	1334809	1			T1	196		T17	1196		T18	3785
valid_sources[0x40]	1628736	1			T1	176		T17	1131		T18	3573
valid_sources[0x41]	1321082	1			T1	213		T17	1099		T18	3901
valid_sources[0x42]	2221273	1			T1	176		T17	1170		T18	3551
valid_sources[0x43]	1327165	1			T1	194		T17	1164		T18	3627
valid_sources[0x44]	1327385	1			T1	164		T17	1068		T18	3560
valid_sources[0x45]	1773223	1			T1	189		T17	972		T18	3604
valid_sources[0x46]	1325861	1			T1	208		T17	1160		T18	3180
valid_sources[0x47]	3270637	1			T1	210		T17	1094		T18	3757
valid_sources[0x48]	4389199	1			T1	196		T17	1177		T18	3780
valid_sources[0x49]	1369344	1			T1	193		T17	1034		T18	3879
valid_sources[0x4a]	1337188	1			T1	202		T17	1094		T18	3521
valid_sources[0x4b]	1323984	1			T1	199		T17	1239		T18	3633
valid_sources[0x4c]	1326541	1			T1	195		T17	1168		T18	3483
valid_sources[0x4d]	2177944	1			T1	168		T17	1113		T18	3495
valid_sources[0x4e]	1324814	1			T1	170		T17	1169		T18	3207
valid_sources[0x4f]	1335907	1			T1	195		T17	1149		T18	3680
valid_sources[0x50]	1321999	1			T1	166		T17	1079		T18	3313
valid_sources[0x51]	1331638	1			T1	179		T17	1050		T18	3699
valid_sources[0x52]	1332070	1			T1	189		T17	1140		T18	3636
valid_sources[0x53]	1324426	1			T1	183		T17	1125		T18	3952
valid_sources[0x54]	1335792	1			T1	174		T17	1044		T18	3700
valid_sources[0x55]	1470422	1			T1	185		T17	1016		T18	3814
valid_sources[0x56]	1429134	1			T1	209		T17	1109		T18	3316
valid_sources[0x57]	1336191	1			T1	180		T17	1045		T18	3533
valid_sources[0x58]	3700752	1			T1	192		T17	1136		T18	3154
valid_sources[0x59]	1403000	1			T1	164		T17	1175		T18	3358
valid_sources[0x5a]	1336305	1			T1	184		T17	1155		T18	3639
valid_sources[0x5b]	1332416	1			T1	187		T17	1192		T18	3803
valid_sources[0x5c]	1354162	1			T1	186		T17	1210		T18	3444
valid_sources[0x5d]	1337856	1			T1	206		T17	1139		T18	3505
valid_sources[0x5e]	1995328	1			T1	226		T17	1172		T18	3433
valid_sources[0x5f]	2222284	1			T1	192		T17	1160		T18	3618
valid_sources[0x60]	1329685	1			T1	197		T17	1057		T18	3163
valid_sources[0x61]	3297649	1			T1	182		T17	1101		T18	3352
valid_sources[0x62]	1325920	1			T1	191		T17	1064		T18	3622
valid_sources[0x63]	3326784	1			T1	172		T17	1092		T18	3431
valid_sources[0x64]	1331512	1			T1	191		T17	1109		T18	3189
valid_sources[0x65]	2305720	1			T1	186		T17	1123		T18	3842
valid_sources[0x66]	2346340	1			T1	186		T17	1186		T18	3432
valid_sources[0x67]	1328975	1			T1	197		T17	1069		T18	3299
valid_sources[0x68]	1330760	1			T1	194		T17	1141		T18	3541
valid_sources[0x69]	1338174	1			T1	209		T17	1050		T18	3651
valid_sources[0x6a]	1359546	1			T1	215		T17	1033		T18	3139
valid_sources[0x6b]	2234903	1			T1	174		T17	1177		T18	3281
valid_sources[0x6c]	1331878	1			T1	211		T17	1102		T18	3293
valid_sources[0x6d]	1331698	1			T1	195		T17	1211		T18	3410
valid_sources[0x6e]	6121704	1			T1	177		T17	1130		T18	3805
valid_sources[0x6f]	1328569	1			T1	200		T17	1132		T18	3721
valid_sources[0x70]	1333806	1			T1	181		T17	1148		T18	3324
valid_sources[0x71]	1335598	1			T1	184		T17	1081		T18	3515
valid_sources[0x72]	2011825	1			T1	204		T17	1177		T18	3394
valid_sources[0x73]	1821953	1			T1	184		T17	1072		T18	3556
valid_sources[0x74]	1328360	1			T1	187		T2	165		T17	1151
valid_sources[0x75]	2544548	1			T1	186		T17	1247		T18	3742
valid_sources[0x76]	1324632	1			T1	202		T17	1139		T18	3491
valid_sources[0x77]	1474747	1			T1	189		T17	1119		T18	3667
valid_sources[0x78]	1361959	1			T1	210		T17	1038		T18	3896
valid_sources[0x79]	2752707	1			T1	197		T17	1081		T18	3383
valid_sources[0x7a]	1335543	1			T1	193		T17	1009		T18	3546
valid_sources[0x7b]	1337974	1			T1	187		T17	1168		T18	3064
valid_sources[0x7c]	3689385	1			T1	202		T17	1126		T18	3524
valid_sources[0x7d]	1333985	1			T1	151		T17	1019		T18	3200
valid_sources[0x7e]	1336138	1			T1	176		T17	1164		T18	3738
valid_sources[0x7f]	1355139	1			T1	205		T17	1122		T18	3531
valid_sources[0x80]	3278290	1			T1	201		T17	1128		T18	3695

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71792030

1

T1

76040

T2

71

T3

1

values[0x0]

all_enables

biggest_size

61295138

1

T1

61862

T2

43

T3

1

values[0x1]

all_enables

biggest_size

52823360

1

T1

52999

T2

37

T3

2