Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262384806

1

T1

282506

T2

14

T3

22

full_word

185967445

1

T1

190901

T2

151

T3

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	448351941	1			T1	473407		T2	165		T3	26
auto[TlIntgErrCmd]	88	1			T134	2		T135	2		T136	4
auto[TlIntgErrData]	108	1			T134	3		T135	2		T136	4
auto[TlIntgErrBoth]	114	1			T134	5		T135	6		T136	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

232296514

1

T1

251541

T2

74

T3

1

auto[1]

216055737

1

T1

221866

T2

91

T3

25

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	160490071	1			T1	175501		T2	3		T17	43323
auto[TlIntgErrNone]	partial	auto[1]	101894445	1			T1	107005		T2	11		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	71806310	1			T1	76040		T2	71		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	114161115	1			T1	114861		T2	80		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T135	1		T136	2		T178	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T134	2		T135	1		T136	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T183	1		T185	1		T186	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T181	1		T187	1		T188	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T134	3		T136	2		T178	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T135	1		T136	2		T178	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T135	1		T187	1		T189	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T179	1		T190	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T134	3		T135	3		T178	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T134	2		T135	2		T136	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T135	1		T179	1		T187	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T180	1		T183	1		T181	1