Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	209790	0	0
entropy_period_rd_A	2147483647	1359	0	0
intr_enable_rd_A	2147483647	1902	0	0
prefix_0_rd_A	2147483647	1373	0	0
prefix_10_rd_A	2147483647	1330	0	0
prefix_1_rd_A	2147483647	1337	0	0
prefix_2_rd_A	2147483647	1313	0	0
prefix_3_rd_A	2147483647	1303	0	0
prefix_4_rd_A	2147483647	1297	0	0
prefix_5_rd_A	2147483647	1252	0	0
prefix_6_rd_A	2147483647	1223	0	0
prefix_7_rd_A	2147483647	1314	0	0
prefix_8_rd_A	2147483647	1235	0	0
prefix_9_rd_A	2147483647	1445	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	209790	0	0
T25	0	113460	0	0
T47	309624	39004	0	0
T48	0	9107	0	0
T83	2739	0	0	0
T90	250987	0	0	0
T134	0	3	0	0
T140	0	19186	0	0
T141	0	26105	0	0
T142	0	152	0	0
T143	0	5	0	0
T144	0	199	0	0
T145	0	243	0	0
T147	95492	0	0	0
T148	2716	0	0	0
T149	493727	0	0	0
T150	51355	0	0	0
T151	107882	0	0	0
T152	220022	0	0	0
T153	10468	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1359	0	0
T95	13290	89	0	0
T97	5737	32	0	0
T98	6050	15	0	0
T104	12201	71	0	0
T134	11844	63	0	0
T135	12510	96	0	0
T164	2991	8	0	0
T165	1719	8	0	0
T166	3076	8	0	0
T167	5627	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T95	13290	71	0	0
T97	5737	43	0	0
T98	6050	5	0	0
T134	11844	63	0	0
T135	12510	66	0	0
T164	2991	31	0	0
T165	1719	3	0	0
T166	3076	22	0	0
T168	998	15	0	0
T169	6875	14	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1373	0	0
T95	13290	46	0	0
T97	5737	27	0	0
T98	6050	12	0	0
T104	12201	53	0	0
T134	11844	50	0	0
T135	12510	39	0	0
T164	2991	12	0	0
T166	3076	5	0	0
T167	5627	48	0	0
T169	6875	14	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1330	0	0
T95	13290	37	0	0
T97	5737	29	0	0
T98	6050	13	0	0
T134	11844	48	0	0
T135	12510	21	0	0
T164	2991	12	0	0
T165	1719	2	0	0
T166	3076	7	0	0
T167	5627	11	0	0
T169	6875	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1337	0	0
T95	13290	54	0	0
T97	5737	18	0	0
T98	6050	11	0	0
T134	11844	47	0	0
T135	12510	60	0	0
T164	2991	7	0	0
T165	1719	7	0	0
T166	3076	8	0	0
T167	5627	11	0	0
T169	6875	10	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T95	13290	63	0	0
T97	5737	19	0	0
T98	6050	5	0	0
T134	11844	31	0	0
T135	12510	45	0	0
T164	2991	8	0	0
T165	1719	8	0	0
T166	3076	6	0	0
T167	5627	37	0	0
T169	6875	22	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1303	0	0
T95	13290	69	0	0
T97	5737	21	0	0
T98	6050	13	0	0
T134	11844	24	0	0
T135	12510	19	0	0
T164	2991	5	0	0
T165	1719	8	0	0
T166	3076	6	0	0
T167	5627	11	0	0
T169	6875	28	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1297	0	0
T95	13290	37	0	0
T97	5737	26	0	0
T98	6050	1	0	0
T104	12201	51	0	0
T134	11844	18	0	0
T135	12510	34	0	0
T164	2991	9	0	0
T166	3076	8	0	0
T167	5627	28	0	0
T169	6875	24	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1252	0	0
T95	13290	46	0	0
T97	5737	36	0	0
T98	6050	10	0	0
T104	12201	60	0	0
T134	11844	48	0	0
T135	12510	34	0	0
T164	2991	2	0	0
T166	3076	1	0	0
T167	5627	12	0	0
T169	6875	20	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223	0	0
T95	13290	68	0	0
T97	5737	14	0	0
T98	6050	10	0	0
T134	11844	35	0	0
T135	12510	52	0	0
T164	2991	6	0	0
T165	1719	6	0	0
T166	3076	3	0	0
T167	5627	1	0	0
T169	6875	8	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1314	0	0
T95	13290	55	0	0
T97	5737	29	0	0
T98	6050	5	0	0
T134	11844	58	0	0
T135	12510	50	0	0
T164	2991	5	0	0
T165	1719	6	0	0
T166	3076	5	0	0
T167	5627	22	0	0
T169	6875	13	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1235	0	0
T95	13290	43	0	0
T97	5737	29	0	0
T98	6050	10	0	0
T134	11844	43	0	0
T135	12510	37	0	0
T164	2991	7	0	0
T165	1719	6	0	0
T166	3076	10	0	0
T167	5627	37	0	0
T169	6875	17	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1445	0	0
T95	13290	40	0	0
T97	5737	19	0	0
T98	6050	8	0	0
T134	11844	40	0	0
T135	12510	62	0	0
T164	2991	9	0	0
T165	1719	6	0	0
T166	3076	18	0	0
T167	5627	30	0	0
T169	6875	11	0	0