Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258707700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182751001

1

T1

251560

T2

926267

T3

251740

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229854357	1			T1	333037		T2	119737		T3	327533
values[0x0]	101729146	1			T1	157844		T2	562658		T3	155827
values[0x1]	109875198	1			T1	172289		T2	614397		T3	168789

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201003359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240455342

1

T1

343429

T2

124858

T3

339387

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3645598	1			T2	9344		T3	2549		T34	11
valid_sources[0x01]	1275972	1			T2	9434		T3	2574		T34	7
valid_sources[0x02]	1399682	1			T2	9061		T3	2521		T34	9
valid_sources[0x03]	1290983	1			T2	9383		T3	2604		T34	3
valid_sources[0x04]	3100816	1			T2	9370		T3	2537		T34	13
valid_sources[0x05]	1280883	1			T2	9404		T3	2550		T34	3
valid_sources[0x06]	2778401	1			T1	663170		T2	9252		T3	2466
valid_sources[0x07]	1278866	1			T2	9500		T3	2572		T34	8
valid_sources[0x08]	1364270	1			T2	9277		T3	2601		T34	6
valid_sources[0x09]	5254880	1			T2	9371		T3	2551		T37	195690
valid_sources[0x0a]	1395786	1			T2	9141		T3	2511		T34	7
valid_sources[0x0b]	3631203	1			T2	9270		T3	2572		T34	3
valid_sources[0x0c]	2622457	1			T2	9238		T3	2606		T34	5
valid_sources[0x0d]	1477670	1			T2	9476		T3	2639		T34	10
valid_sources[0x0e]	1284822	1			T2	9526		T3	2443		T34	3
valid_sources[0x0f]	3653063	1			T2	9232		T3	2607		T34	4
valid_sources[0x10]	3641673	1			T2	9269		T3	2456		T34	5
valid_sources[0x11]	1327678	1			T2	9248		T3	2713		T34	6
valid_sources[0x12]	1281339	1			T2	9256		T3	2609		T34	11
valid_sources[0x13]	1278212	1			T2	9272		T3	2595		T34	5
valid_sources[0x14]	1714627	1			T2	9357		T3	2603		T34	9
valid_sources[0x15]	1277222	1			T2	9381		T3	2530		T34	9
valid_sources[0x16]	2185569	1			T2	9377		T3	2571		T34	3
valid_sources[0x17]	1286453	1			T2	9182		T3	2560		T34	2
valid_sources[0x18]	1278069	1			T2	9087		T3	2532		T34	8
valid_sources[0x19]	1286943	1			T2	9104		T3	2569		T34	5
valid_sources[0x1a]	2252263	1			T2	9274		T3	2582		T34	5
valid_sources[0x1b]	1281540	1			T2	9103		T3	2529		T34	4
valid_sources[0x1c]	1368574	1			T2	9408		T3	2598		T34	6
valid_sources[0x1d]	1294280	1			T2	9183		T3	2534		T34	7
valid_sources[0x1e]	2182625	1			T2	9079		T3	2458		T34	2
valid_sources[0x1f]	1277547	1			T2	9282		T3	2525		T34	8
valid_sources[0x20]	1274059	1			T2	8896		T3	2590		T34	7
valid_sources[0x21]	1281546	1			T2	9330		T3	2498		T34	12
valid_sources[0x22]	1284481	1			T2	9410		T3	2555		T34	6
valid_sources[0x23]	5553409	1			T2	9446		T3	2543		T34	13
valid_sources[0x24]	1288962	1			T2	9356		T3	2442		T34	3
valid_sources[0x25]	1280803	1			T2	9277		T3	2584		T34	6
valid_sources[0x26]	1388680	1			T2	9407		T3	2490		T34	9
valid_sources[0x27]	2235682	1			T2	9422		T3	2581		T34	1
valid_sources[0x28]	1280480	1			T2	9278		T3	2600		T34	5
valid_sources[0x29]	1279728	1			T2	9468		T3	2505		T34	13
valid_sources[0x2a]	1274814	1			T2	9209		T3	2513		T34	10
valid_sources[0x2b]	3639470	1			T2	9325		T3	2588		T34	3
valid_sources[0x2c]	1307553	1			T2	9238		T3	2558		T34	8
valid_sources[0x2d]	1284065	1			T2	9270		T3	2560		T34	3
valid_sources[0x2e]	1283353	1			T2	9298		T3	2517		T34	9
valid_sources[0x2f]	1287329	1			T2	9544		T3	2565		T34	13
valid_sources[0x30]	1681609	1			T2	9158		T3	2562		T34	8
valid_sources[0x31]	1277274	1			T2	9191		T3	2561		T34	6
valid_sources[0x32]	1283011	1			T2	9339		T3	2497		T34	5
valid_sources[0x33]	1277590	1			T2	9408		T3	2551		T34	7
valid_sources[0x34]	3625080	1			T2	9010		T3	2453		T34	1
valid_sources[0x35]	1275762	1			T2	9499		T3	2543		T34	4
valid_sources[0x36]	1275930	1			T2	9219		T3	2453		T34	11
valid_sources[0x37]	1277655	1			T2	9186		T3	2522		T34	7
valid_sources[0x38]	1281031	1			T2	9170		T3	2556		T34	7
valid_sources[0x39]	1280253	1			T2	9255		T3	2551		T34	5
valid_sources[0x3a]	1276465	1			T2	9241		T3	2484		T34	2
valid_sources[0x3b]	2302280	1			T2	9289		T3	2511		T34	7
valid_sources[0x3c]	1370047	1			T2	9290		T3	2613		T34	13
valid_sources[0x3d]	1283230	1			T2	9405		T3	2550		T34	13
valid_sources[0x3e]	1466035	1			T2	9243		T3	2653		T34	8
valid_sources[0x3f]	1281495	1			T2	9246		T3	2546		T34	3
valid_sources[0x40]	1277059	1			T2	8977		T3	2483		T34	4
valid_sources[0x41]	1272189	1			T2	9262		T3	2559		T34	5
valid_sources[0x42]	1457387	1			T2	9281		T3	2545		T34	9
valid_sources[0x43]	2832742	1			T2	9551		T3	2556		T34	6
valid_sources[0x44]	1276285	1			T2	9266		T3	2580		T34	13
valid_sources[0x45]	1283396	1			T2	9220		T3	2508		T34	2
valid_sources[0x46]	2063793	1			T2	9280		T3	2529		T34	6
valid_sources[0x47]	3248136	1			T2	9556		T3	2555		T34	8
valid_sources[0x48]	2176454	1			T2	9298		T3	2503		T34	7
valid_sources[0x49]	1278198	1			T2	9397		T3	2558		T34	9
valid_sources[0x4a]	1733892	1			T2	8954		T3	2590		T34	10
valid_sources[0x4b]	1282862	1			T2	9262		T3	2491		T34	7
valid_sources[0x4c]	1372514	1			T2	9540		T3	2546		T34	1
valid_sources[0x4d]	1409631	1			T2	9114		T3	2571		T34	7
valid_sources[0x4e]	2070989	1			T2	9357		T3	2448		T34	12
valid_sources[0x4f]	1362963	1			T2	9339		T3	2551		T34	5
valid_sources[0x50]	1942225	1			T2	9309		T3	2453		T34	3
valid_sources[0x51]	1278830	1			T2	9454		T3	2490		T34	3
valid_sources[0x52]	1739008	1			T2	9431		T3	2573		T35	6
valid_sources[0x53]	1283633	1			T2	9283		T3	2500		T34	6
valid_sources[0x54]	1275017	1			T2	9158		T3	2446		T34	5
valid_sources[0x55]	1277139	1			T2	9304		T3	2664		T34	1
valid_sources[0x56]	1312038	1			T2	9213		T3	2492		T34	5
valid_sources[0x57]	1289144	1			T2	9343		T3	2694		T34	4
valid_sources[0x58]	1273793	1			T2	9417		T3	2466		T34	2
valid_sources[0x59]	1271199	1			T2	9485		T3	2555		T34	10
valid_sources[0x5a]	3210026	1			T2	9096		T3	2560		T34	2
valid_sources[0x5b]	1287579	1			T2	9350		T3	2682		T34	3
valid_sources[0x5c]	1303835	1			T2	9344		T3	2570		T34	6
valid_sources[0x5d]	1408519	1			T2	9278		T3	2705		T34	4
valid_sources[0x5e]	1621603	1			T2	9442		T3	2622		T34	7
valid_sources[0x5f]	1282596	1			T2	9298		T3	2503		T34	5
valid_sources[0x60]	1347396	1			T2	9516		T3	2428		T34	14
valid_sources[0x61]	1953395	1			T2	9118		T3	2547		T34	5
valid_sources[0x62]	1727282	1			T2	9385		T3	2547		T34	6
valid_sources[0x63]	1744104	1			T2	9154		T3	2562		T34	17
valid_sources[0x64]	3236363	1			T2	9181		T3	2587		T34	5
valid_sources[0x65]	1277882	1			T2	9364		T3	2525		T34	7
valid_sources[0x66]	1362391	1			T2	9195		T3	2627		T34	6
valid_sources[0x67]	2058578	1			T2	9183		T3	2549		T34	3
valid_sources[0x68]	1275701	1			T2	9216		T3	2646		T34	9
valid_sources[0x69]	2106177	1			T2	9008		T3	2610		T34	13
valid_sources[0x6a]	1670169	1			T2	9456		T3	2579		T34	7
valid_sources[0x6b]	2128439	1			T2	9078		T3	2470		T34	8
valid_sources[0x6c]	2179314	1			T2	9540		T3	2601		T34	9
valid_sources[0x6d]	3190257	1			T2	9504		T3	2475		T34	9
valid_sources[0x6e]	1283461	1			T2	9421		T3	2517		T34	7
valid_sources[0x6f]	1299960	1			T2	8951		T3	2459		T34	11
valid_sources[0x70]	1276761	1			T2	9192		T3	2601		T34	5
valid_sources[0x71]	3259950	1			T2	9385		T3	2479		T34	6
valid_sources[0x72]	1280013	1			T2	9127		T3	2640		T34	9
valid_sources[0x73]	2225798	1			T2	9257		T3	2588		T34	2
valid_sources[0x74]	3260486	1			T2	9279		T3	2553		T34	7
valid_sources[0x75]	1279897	1			T2	9199		T3	2650		T34	3
valid_sources[0x76]	2120185	1			T2	9248		T3	2561		T34	5
valid_sources[0x77]	1278359	1			T2	9163		T3	2624		T34	4
valid_sources[0x78]	3572478	1			T2	9333		T3	2545		T34	2
valid_sources[0x79]	1277413	1			T2	9146		T3	2599		T34	7
valid_sources[0x7a]	1283905	1			T2	9406		T3	2614		T34	5
valid_sources[0x7b]	1285052	1			T2	9371		T3	2552		T34	2
valid_sources[0x7c]	1275289	1			T2	9265		T3	2514		T34	4
valid_sources[0x7d]	1284649	1			T2	9147		T3	2541		T34	6
valid_sources[0x7e]	1281546	1			T2	9464		T3	2518		T34	3
valid_sources[0x7f]	1349430	1			T2	9410		T3	2505		T34	9
valid_sources[0x80]	1270221	1			T2	9268		T3	2561		T34	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70670334

1

T1

88784

T2

340090

T3

87611

values[0x0]

all_enables

biggest_size

60204450

1

T1

88414

T2

316814

T3

88953

values[0x1]

all_enables

biggest_size

51876217

1

T1

74362

T2

269363

T3

75176