Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258891805

1

T1

411610

T2

144816

T3

400409

full_word

182762405

1

T1

251560

T2

926267

T3

251740

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	441653900	1			T1	663170		T2	237442		T3	652149
auto[TlIntgErrCmd]	96	1			T112	3		T153	4		T154	6
auto[TlIntgErrData]	116	1			T112	3		T153	9		T154	5
auto[TlIntgErrBoth]	98	1			T112	4		T153	7		T154	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229890597

1

T1

333037

T2

119737

T3

327533

auto[1]

211763613

1

T1

330133

T2

117705

T3

324616

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159217264	1			T1	244253		T2	857283		T3	239922
auto[TlIntgErrNone]	partial	auto[1]	99674255	1			T1	167357		T2	590878		T3	160487
auto[TlIntgErrNone]	full_word	auto[0]	70673192	1			T1	88784		T2	340090		T3	87611
auto[TlIntgErrNone]	full_word	auto[1]	112089189	1			T1	162776		T2	586177		T3	164129
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T112	1		T153	2		T154	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T112	1		T153	2		T154	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T214	1		T218	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T112	1		T214	1		T219	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T112	1		T153	2		T154	4
auto[TlIntgErrData]	partial	auto[1]	56	1			T112	1		T153	7		T214	5
auto[TlIntgErrData]	full_word	auto[0]	11	1			T112	1		T220	1		T219	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T154	1		T213	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T112	2		T153	4		T154	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T112	2		T153	3		T154	8
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T216	1		T221	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T213	1		-	-		-	-