Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	43162	0	0
entropy_period_rd_A	2147483647	1725	0	0
intr_enable_rd_A	2147483647	1881	0	0
prefix_0_rd_A	2147483647	1429	0	0
prefix_10_rd_A	2147483647	1478	0	0
prefix_1_rd_A	2147483647	1503	0	0
prefix_2_rd_A	2147483647	1523	0	0
prefix_3_rd_A	2147483647	1391	0	0
prefix_4_rd_A	2147483647	1474	0	0
prefix_5_rd_A	2147483647	1513	0	0
prefix_6_rd_A	2147483647	1528	0	0
prefix_7_rd_A	2147483647	1400	0	0
prefix_8_rd_A	2147483647	1412	0	0
prefix_9_rd_A	2147483647	1467	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43162	0	0
T53	340940	33709	0	0
T54	0	5839	0	0
T112	0	1	0	0
T150	0	2	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	164	0	0
T161	0	70	0	0
T163	0	4	0	0
T164	0	119	0	0
T166	2784	0	0	0
T167	531069	0	0	0
T168	876145	0	0	0
T169	340228	0	0	0
T170	865	0	0	0
T171	23914	0	0	0
T172	102124	0	0	0
T173	425408	0	0	0
T174	967459	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1725	0	0
T54	879995	28	0	0
T111	0	50	0	0
T150	0	10	0	0
T151	0	9	0	0
T153	0	149	0	0
T182	0	28	0	0
T183	0	10	0	0
T184	0	3	0	0
T185	0	439	0	0
T186	0	2	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T54	879995	11	0	0
T111	0	57	0	0
T150	0	10	0	0
T153	0	147	0	0
T158	0	12	0	0
T182	0	64	0	0
T183	0	7	0	0
T184	0	5	0	0
T185	0	434	0	0
T186	0	7	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T54	879995	3	0	0
T111	0	35	0	0
T150	0	12	0	0
T151	0	13	0	0
T153	0	72	0	0
T182	0	17	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	464	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	24	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1478	0	0
T54	879995	40	0	0
T111	0	10	0	0
T150	0	4	0	0
T151	0	3	0	0
T153	0	120	0	0
T182	0	41	0	0
T183	0	20	0	0
T184	0	8	0	0
T185	0	457	0	0
T186	0	7	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1503	0	0
T54	879995	42	0	0
T111	0	53	0	0
T150	0	8	0	0
T151	0	4	0	0
T153	0	91	0	0
T182	0	63	0	0
T183	0	21	0	0
T185	0	467	0	0
T186	0	6	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	27	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T54	879995	14	0	0
T111	0	25	0	0
T150	0	10	0	0
T151	0	3	0	0
T153	0	104	0	0
T182	0	59	0	0
T184	0	1	0	0
T185	0	459	0	0
T186	0	4	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	28	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1391	0	0
T54	879995	21	0	0
T111	0	33	0	0
T150	0	3	0	0
T151	0	15	0	0
T153	0	98	0	0
T182	0	39	0	0
T183	0	10	0	0
T184	0	9	0	0
T185	0	433	0	0
T186	0	9	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1474	0	0
T54	879995	18	0	0
T111	0	14	0	0
T150	0	12	0	0
T151	0	13	0	0
T153	0	87	0	0
T182	0	54	0	0
T184	0	7	0	0
T185	0	464	0	0
T186	0	3	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	29	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T54	879995	21	0	0
T111	0	21	0	0
T150	0	9	0	0
T151	0	3	0	0
T152	0	27	0	0
T153	0	85	0	0
T182	0	33	0	0
T185	0	490	0	0
T186	0	9	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	41	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1528	0	0
T54	879995	12	0	0
T111	0	27	0	0
T150	0	10	0	0
T151	0	12	0	0
T153	0	63	0	0
T182	0	35	0	0
T183	0	4	0	0
T185	0	411	0	0
T186	0	4	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0
T196	0	62	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1400	0	0
T54	879995	10	0	0
T111	0	21	0	0
T150	0	2	0	0
T151	0	10	0	0
T153	0	79	0	0
T182	0	40	0	0
T183	0	8	0	0
T184	0	1	0	0
T185	0	378	0	0
T186	0	2	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T54	879995	1	0	0
T111	0	17	0	0
T150	0	1	0	0
T151	0	6	0	0
T153	0	54	0	0
T182	0	46	0	0
T183	0	6	0	0
T184	0	13	0	0
T185	0	500	0	0
T186	0	6	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1467	0	0
T54	879995	10	0	0
T111	0	44	0	0
T150	0	4	0	0
T151	0	9	0	0
T153	0	79	0	0
T182	0	64	0	0
T183	0	29	0	0
T184	0	5	0	0
T185	0	415	0	0
T186	0	4	0	0
T187	11990	0	0	0
T188	197910	0	0	0
T189	94818	0	0	0
T190	26495	0	0	0
T191	669348	0	0	0
T192	120533	0	0	0
T193	152536	0	0	0
T194	483772	0	0	0
T195	175665	0	0	0