Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167505 |
1 |
|
|
T2 |
1265 |
|
T9 |
81 |
|
T18 |
724 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
86530 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60215 |
1 |
|
|
T2 |
842 |
|
T9 |
80 |
|
T18 |
714 |
seven_bytes |
2951 |
1 |
|
|
T2 |
8 |
|
T20 |
28 |
|
T96 |
1 |
six_bytes |
2962 |
1 |
|
|
T2 |
18 |
|
T20 |
32 |
|
T96 |
3 |
five_bytes |
3035 |
1 |
|
|
T2 |
11 |
|
T20 |
41 |
|
T96 |
1 |
four_bytes |
2937 |
1 |
|
|
T2 |
12 |
|
T20 |
20 |
|
T96 |
3 |
three_bytes |
2920 |
1 |
|
|
T2 |
13 |
|
T20 |
34 |
|
T96 |
3 |
two_bytes |
3003 |
1 |
|
|
T2 |
18 |
|
T20 |
30 |
|
T96 |
4 |
one_byte |
2952 |
1 |
|
|
T2 |
7 |
|
T20 |
36 |
|
T96 |
1 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164249 |
1 |
|
|
T2 |
1237 |
|
T9 |
79 |
|
T18 |
704 |
auto[1] |
3256 |
1 |
|
|
T2 |
28 |
|
T9 |
2 |
|
T18 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167505 |
1 |
|
|
T2 |
1265 |
|
T9 |
81 |
|
T18 |
724 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167496 |
1 |
|
|
T2 |
1265 |
|
T9 |
81 |
|
T18 |
724 |
auto[1] |
9 |
1 |
|
|
T22 |
1 |
|
T11 |
1 |
|
T173 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1092 |
1 |
|
|
T2 |
13 |
|
T9 |
1 |
|
T18 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3256 |
1 |
|
|
T2 |
28 |
|
T9 |
2 |
|
T18 |
20 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170410 |
1 |
|
|
T2 |
633 |
|
T18 |
317 |
|
T37 |
170 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87998 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61734 |
1 |
|
|
T2 |
624 |
|
T18 |
312 |
|
T37 |
165 |
seven_bytes |
3007 |
1 |
|
|
T14 |
4 |
|
T20 |
71 |
|
T96 |
8 |
six_bytes |
2938 |
1 |
|
|
T14 |
5 |
|
T20 |
73 |
|
T96 |
14 |
five_bytes |
2948 |
1 |
|
|
T14 |
5 |
|
T20 |
63 |
|
T96 |
2 |
four_bytes |
3018 |
1 |
|
|
T14 |
13 |
|
T20 |
62 |
|
T96 |
9 |
three_bytes |
2892 |
1 |
|
|
T14 |
4 |
|
T20 |
59 |
|
T96 |
9 |
two_bytes |
2849 |
1 |
|
|
T14 |
6 |
|
T20 |
58 |
|
T96 |
9 |
one_byte |
3026 |
1 |
|
|
T14 |
10 |
|
T20 |
56 |
|
T96 |
12 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167092 |
1 |
|
|
T2 |
615 |
|
T18 |
307 |
|
T37 |
160 |
auto[1] |
3318 |
1 |
|
|
T2 |
18 |
|
T18 |
10 |
|
T37 |
10 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170410 |
1 |
|
|
T2 |
633 |
|
T18 |
317 |
|
T37 |
170 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
170399 |
1 |
|
|
T2 |
633 |
|
T18 |
317 |
|
T37 |
170 |
auto[1] |
11 |
1 |
|
|
T72 |
1 |
|
T174 |
1 |
|
T119 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1135 |
1 |
|
|
T2 |
9 |
|
T18 |
5 |
|
T37 |
5 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3318 |
1 |
|
|
T2 |
18 |
|
T18 |
10 |
|
T37 |
10 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339837 |
1 |
|
|
T2 |
2006 |
|
T7 |
3 |
|
T8 |
103 |
auto[1] |
410 |
1 |
|
|
T10 |
92 |
|
T11 |
43 |
|
T12 |
24 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
180325 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
117012 |
1 |
|
|
T2 |
1037 |
|
T7 |
3 |
|
T8 |
100 |
seven_bytes |
6093 |
1 |
|
|
T2 |
29 |
|
T14 |
7 |
|
T20 |
89 |
six_bytes |
6235 |
1 |
|
|
T2 |
24 |
|
T14 |
3 |
|
T20 |
80 |
five_bytes |
6163 |
1 |
|
|
T2 |
30 |
|
T14 |
4 |
|
T20 |
79 |
four_bytes |
6063 |
1 |
|
|
T2 |
23 |
|
T14 |
10 |
|
T20 |
63 |
three_bytes |
6107 |
1 |
|
|
T2 |
26 |
|
T14 |
4 |
|
T20 |
80 |
two_bytes |
6196 |
1 |
|
|
T2 |
28 |
|
T14 |
3 |
|
T20 |
67 |
one_byte |
6053 |
1 |
|
|
T2 |
26 |
|
T14 |
7 |
|
T20 |
61 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333855 |
1 |
|
|
T2 |
1954 |
|
T7 |
3 |
|
T8 |
97 |
auto[1] |
6392 |
1 |
|
|
T2 |
52 |
|
T8 |
6 |
|
T9 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
340247 |
1 |
|
|
T2 |
2006 |
|
T7 |
3 |
|
T8 |
103 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
340220 |
1 |
|
|
T2 |
2006 |
|
T7 |
3 |
|
T8 |
103 |
auto[1] |
27 |
1 |
|
|
T37 |
1 |
|
T67 |
1 |
|
T53 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2203 |
1 |
|
|
T2 |
21 |
|
T8 |
3 |
|
T9 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6392 |
1 |
|
|
T2 |
52 |
|
T8 |
6 |
|
T9 |
8 |