Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260013082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184827583

1

T1

249451

T2

228056

T3

911786

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230790541	1			T1	333355		T2	286276		T3	118247
values[0x0]	102904845	1			T1	156738		T2	94430		T3	551648
values[0x1]	111145279	1			T1	171855		T2	98882		T3	596601

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202120368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242720297

1

T1

341221

T2

289064

T3

122277

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1306641	1			T1	2500		T2	1854		T3	9144
valid_sources[0x01]	2990804	1			T1	2482		T2	1935		T3	8919
valid_sources[0x02]	3203634	1			T1	2476		T2	1866		T3	9259
valid_sources[0x03]	1246605	1			T1	2883		T2	1838		T3	9275
valid_sources[0x04]	1247125	1			T1	2592		T2	1799		T3	9600
valid_sources[0x05]	1452758	1			T1	2563		T2	1905		T3	9370
valid_sources[0x06]	2137250	1			T1	2543		T2	1856		T3	9464
valid_sources[0x07]	1321928	1			T1	2569		T2	1817		T3	9381
valid_sources[0x08]	1246652	1			T1	2446		T2	1960		T3	8906
valid_sources[0x09]	1907757	1			T1	2752		T2	1878		T3	9291
valid_sources[0x0a]	1243150	1			T1	2582		T2	1857		T3	8935
valid_sources[0x0b]	1255324	1			T1	2674		T2	1893		T3	8709
valid_sources[0x0c]	1238922	1			T1	2642		T2	1959		T3	9023
valid_sources[0x0d]	3241197	1			T1	2567		T2	1922		T3	9149
valid_sources[0x0e]	1253332	1			T1	2675		T2	1875		T3	9089
valid_sources[0x0f]	1338586	1			T1	2482		T2	1900		T3	9233
valid_sources[0x10]	1244601	1			T1	2449		T2	1921		T3	8804
valid_sources[0x11]	1265859	1			T1	2820		T2	1933		T3	8919
valid_sources[0x12]	4430462	1			T1	2536		T2	1884		T3	8841
valid_sources[0x13]	1242373	1			T1	2331		T2	1896		T3	9290
valid_sources[0x14]	2143513	1			T1	2873		T2	1894		T3	9337
valid_sources[0x15]	3591660	1			T1	2333		T2	1942		T3	9509
valid_sources[0x16]	1506450	1			T1	2799		T2	1841		T3	9515
valid_sources[0x17]	2995874	1			T1	2419		T2	1890		T3	9403
valid_sources[0x18]	1237526	1			T1	2403		T2	1913		T3	8931
valid_sources[0x19]	1245400	1			T1	2724		T2	1909		T3	8989
valid_sources[0x1a]	1247261	1			T1	2485		T2	1852		T3	8830
valid_sources[0x1b]	1693236	1			T1	2829		T2	1875		T3	9415
valid_sources[0x1c]	1240711	1			T1	2699		T2	1927		T3	9071
valid_sources[0x1d]	3223832	1			T1	2187		T2	1917		T3	9029
valid_sources[0x1e]	1373804	1			T1	2827		T2	1921		T3	8879
valid_sources[0x1f]	1811976	1			T1	2720		T2	1885		T3	9111
valid_sources[0x20]	2605468	1			T1	2517		T2	1901		T3	9322
valid_sources[0x21]	1274470	1			T1	2839		T2	1869		T3	9312
valid_sources[0x22]	3002099	1			T1	2887		T2	1859		T3	9379
valid_sources[0x23]	1246194	1			T1	2492		T2	1837		T3	8525
valid_sources[0x24]	1252933	1			T1	2740		T2	1838		T3	8463
valid_sources[0x25]	1898030	1			T1	2616		T2	1904		T3	8378
valid_sources[0x26]	2098364	1			T1	3103		T2	1906		T3	8962
valid_sources[0x27]	1280335	1			T1	2295		T2	1881		T3	8552
valid_sources[0x28]	1240698	1			T1	2529		T2	1866		T3	8762
valid_sources[0x29]	1244546	1			T1	2603		T2	1868		T3	8913
valid_sources[0x2a]	3559310	1			T1	2685		T2	1933		T3	9643
valid_sources[0x2b]	1248261	1			T1	2698		T2	1818		T3	9097
valid_sources[0x2c]	1249389	1			T1	2595		T2	1927		T3	9152
valid_sources[0x2d]	1698658	1			T1	2613		T2	1722		T3	9338
valid_sources[0x2e]	1282576	1			T1	2413		T2	1866		T3	9191
valid_sources[0x2f]	1294548	1			T1	2452		T2	1824		T3	9197
valid_sources[0x30]	1889289	1			T1	2735		T2	1934		T3	8482
valid_sources[0x31]	1246112	1			T1	2621		T2	1926		T3	8766
valid_sources[0x32]	1241143	1			T1	2571		T2	1820		T3	8990
valid_sources[0x33]	1250343	1			T1	2847		T2	1904		T3	9016
valid_sources[0x34]	1464525	1			T1	2721		T2	1880		T3	9564
valid_sources[0x35]	1243757	1			T1	2570		T2	1890		T3	9053
valid_sources[0x36]	2104160	1			T1	2527		T2	1777		T3	9185
valid_sources[0x37]	1235322	1			T1	2522		T2	1812		T3	9460
valid_sources[0x38]	5586537	1			T1	2402		T2	1876		T3	9303
valid_sources[0x39]	4342476	1			T1	2649		T2	1856		T3	9185
valid_sources[0x3a]	1261205	1			T1	2656		T2	1843		T3	8958
valid_sources[0x3b]	3210199	1			T1	2421		T2	1923		T3	8890
valid_sources[0x3c]	1365372	1			T1	2562		T2	1881		T3	9133
valid_sources[0x3d]	1246170	1			T1	2139		T2	1909		T3	9200
valid_sources[0x3e]	1243482	1			T1	2320		T2	1895		T3	8722
valid_sources[0x3f]	1240039	1			T1	2427		T2	1886		T3	9539
valid_sources[0x40]	2137844	1			T1	2583		T2	1848		T3	8883
valid_sources[0x41]	2095470	1			T1	2943		T2	1930		T3	9429
valid_sources[0x42]	2548280	1			T1	2441		T2	1823		T3	9124
valid_sources[0x43]	2145471	1			T1	2740		T2	2014		T3	8852
valid_sources[0x44]	2074695	1			T1	2186		T2	1871		T3	8919
valid_sources[0x45]	2137825	1			T1	2579		T2	1888		T3	8803
valid_sources[0x46]	3215903	1			T1	2197		T2	1810		T3	9463
valid_sources[0x47]	1239030	1			T1	2613		T2	1932		T3	8922
valid_sources[0x48]	1242651	1			T1	2689		T2	1815		T3	9133
valid_sources[0x49]	1249152	1			T1	2440		T2	1857		T3	8813
valid_sources[0x4a]	1273249	1			T1	2389		T2	1939		T3	8746
valid_sources[0x4b]	1266568	1			T1	2760		T2	1916		T3	9400
valid_sources[0x4c]	1249226	1			T1	3017		T2	1913		T3	9104
valid_sources[0x4d]	3574883	1			T1	2721		T2	1947		T3	9030
valid_sources[0x4e]	1924644	1			T1	2359		T2	1861		T3	9200
valid_sources[0x4f]	1240575	1			T1	2488		T2	1803		T3	8536
valid_sources[0x50]	3580182	1			T1	2310		T2	1816		T3	9159
valid_sources[0x51]	8341374	1			T1	2257		T2	1842		T3	8743
valid_sources[0x52]	2103214	1			T1	2890		T2	1857		T3	8510
valid_sources[0x53]	1244571	1			T1	2573		T2	1846		T3	9423
valid_sources[0x54]	1239572	1			T1	2743		T2	1875		T3	9229
valid_sources[0x55]	2997713	1			T1	2520		T2	1940		T3	8962
valid_sources[0x56]	1380830	1			T1	2554		T2	1875		T3	8954
valid_sources[0x57]	3245341	1			T1	2537		T2	1869		T3	9224
valid_sources[0x58]	1719749	1			T1	2614		T2	1829		T3	8981
valid_sources[0x59]	1892133	1			T1	2489		T2	1858		T3	9270
valid_sources[0x5a]	1721213	1			T1	2767		T2	1791		T3	9212
valid_sources[0x5b]	3618734	1			T1	2551		T2	1935		T3	9041
valid_sources[0x5c]	1269878	1			T1	2616		T2	1833		T3	9362
valid_sources[0x5d]	2107971	1			T1	2359		T2	1864		T3	9241
valid_sources[0x5e]	3559865	1			T1	2662		T2	1817		T3	8972
valid_sources[0x5f]	1251124	1			T1	2876		T2	1798		T3	9095
valid_sources[0x60]	1243922	1			T1	2417		T2	1886		T3	8917
valid_sources[0x61]	1684990	1			T1	2680		T2	1863		T3	9100
valid_sources[0x62]	1245003	1			T1	2736		T2	1855		T3	9025
valid_sources[0x63]	1418951	1			T1	2672		T2	1888		T3	8959
valid_sources[0x64]	4502843	1			T1	2699		T2	1892		T3	8944
valid_sources[0x65]	1241343	1			T1	2801		T2	1856		T3	9167
valid_sources[0x66]	1242293	1			T1	2461		T2	1815		T3	8949
valid_sources[0x67]	2073838	1			T1	2670		T2	1914		T3	9264
valid_sources[0x68]	1247429	1			T1	2933		T2	1843		T3	8937
valid_sources[0x69]	1246420	1			T1	2824		T2	1889		T3	9178
valid_sources[0x6a]	1348776	1			T1	2788		T2	1874		T3	9485
valid_sources[0x6b]	1252712	1			T1	2763		T2	2008		T3	9216
valid_sources[0x6c]	3222652	1			T1	2609		T2	1872		T3	8875
valid_sources[0x6d]	1769188	1			T1	2857		T2	1973		T3	9053
valid_sources[0x6e]	1244033	1			T1	2829		T2	1820		T3	9337
valid_sources[0x6f]	1361449	1			T1	2643		T2	1789		T3	9096
valid_sources[0x70]	3684660	1			T1	2465		T2	1853		T3	9024
valid_sources[0x71]	1236097	1			T1	2554		T2	1927		T3	8917
valid_sources[0x72]	1245009	1			T1	2778		T2	1888		T3	9069
valid_sources[0x73]	1240130	1			T1	2494		T2	1904		T3	9280
valid_sources[0x74]	1282885	1			T1	2726		T2	1937		T3	8662
valid_sources[0x75]	1268774	1			T1	2887		T2	1815		T3	8912
valid_sources[0x76]	1240368	1			T1	2578		T2	1799		T3	8976
valid_sources[0x77]	1695565	1			T1	2687		T2	1889		T3	9728
valid_sources[0x78]	1246534	1			T1	2827		T2	1875		T3	9638
valid_sources[0x79]	1240938	1			T1	2305		T2	1915		T3	9049
valid_sources[0x7a]	1726391	1			T1	2454		T2	1833		T3	9267
valid_sources[0x7b]	1930142	1			T1	2399		T2	1917		T3	9341
valid_sources[0x7c]	1369466	1			T1	2379		T2	1885		T3	9603
valid_sources[0x7d]	1286682	1			T1	2511		T2	1898		T3	9189
valid_sources[0x7e]	3308382	1			T1	2691		T2	1757		T3	9065
valid_sources[0x7f]	1244193	1			T1	2678		T2	1905		T3	8806
valid_sources[0x80]	2150310	1			T1	2385		T2	1806		T3	9048

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71475165

1

T1

89010

T2

96905

T3

336819

values[0x0]

all_enables

biggest_size

60900663

1

T1

87352

T2

68441

T3

311702

values[0x1]

all_enables

biggest_size

52451755

1

T1

73089

T2

62710

T3

263265