Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

261028721

1

T1

412497

T2

251532

T3

141893

full_word

184891739

1

T1

249451

T2

228056

T3

911786

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	445920180	1			T1	661948		T2	479588		T3	233072
auto[TlIntgErrCmd]	91	1			T121	1		T122	3		T123	8
auto[TlIntgErrData]	95	1			T121	6		T122	6		T123	6
auto[TlIntgErrBoth]	94	1			T121	3		T122	11		T123	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230990192

1

T1

333355

T2

286276

T3

118247

auto[1]

214930268

1

T1

328593

T2

193312

T3

114824

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159498536	1			T1	244345		T2	189371		T3	845654
auto[TlIntgErrNone]	partial	auto[1]	101529921	1			T1	168152		T2	62161		T3	573282
auto[TlIntgErrNone]	full_word	auto[0]	71491518	1			T1	89010		T2	96905		T3	336819
auto[TlIntgErrNone]	full_word	auto[1]	113400205	1			T1	160441		T2	131151		T3	574967
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T121	1		T122	1		T123	4
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T122	2		T123	3		T178	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T176	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T123	1		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T121	3		T122	4		T123	2
auto[TlIntgErrData]	partial	auto[1]	39	1			T121	2		T122	2		T123	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T181	1		T182	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T121	1		T178	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T122	2		T123	3		T178	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T121	3		T122	9		T123	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T185	1		T186	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T179	1		-	-		-	-