Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	237220	0	0
entropy_period_rd_A	2147483647	1177	0	0
intr_enable_rd_A	2147483647	2065	0	0
prefix_0_rd_A	2147483647	1187	0	0
prefix_10_rd_A	2147483647	1195	0	0
prefix_1_rd_A	2147483647	1147	0	0
prefix_2_rd_A	2147483647	1162	0	0
prefix_3_rd_A	2147483647	1225	0	0
prefix_4_rd_A	2147483647	1068	0	0
prefix_5_rd_A	2147483647	1241	0	0
prefix_6_rd_A	2147483647	1144	0	0
prefix_7_rd_A	2147483647	1171	0	0
prefix_8_rd_A	2147483647	1093	0	0
prefix_9_rd_A	2147483647	1142	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	237220	0	0
T24	172138	26801	0	0
T60	0	57194	0	0
T61	0	150313	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T127	0	231	0	0
T128	0	272	0	0
T129	0	2	0	0
T130	0	46	0	0
T132	471179	0	0	0
T133	39253	0	0	0
T134	14139	0	0	0
T135	208999	0	0	0
T136	18608	0	0	0
T137	208846	0	0	0
T138	525705	0	0	0
T139	998	0	0	0
T140	350234	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1177	0	0
T82	4851	15	0	0
T87	11062	73	0	0
T93	5206	9	0	0
T122	20649	82	0	0
T155	73031	98	0	0
T156	8751	21	0	0
T157	3239	9	0	0
T158	7507	20	0	0
T159	10752	4	0	0
T160	3328	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2065	0	0
T82	4851	18	0	0
T87	11062	103	0	0
T122	20649	87	0	0
T126	2095	10	0	0
T155	73031	285	0	0
T161	1262	3	0	0
T162	1369	5	0	0
T163	1150	17	0	0
T164	910	12	0	0
T165	1317	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1187	0	0
T82	4851	20	0	0
T87	11062	52	0	0
T93	5206	5	0	0
T122	20649	50	0	0
T155	73031	216	0	0
T156	8751	24	0	0
T157	3239	7	0	0
T158	7507	23	0	0
T166	12230	10	0	0
T167	7444	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1195	0	0
T82	4851	18	0	0
T87	11062	50	0	0
T93	5206	9	0	0
T122	20649	23	0	0
T155	73031	242	0	0
T156	8751	6	0	0
T158	7507	12	0	0
T160	3328	10	0	0
T168	11130	51	0	0
T169	7691	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1147	0	0
T82	4851	30	0	0
T87	11062	61	0	0
T93	5206	14	0	0
T122	20649	30	0	0
T155	73031	260	0	0
T156	8751	9	0	0
T157	3239	10	0	0
T158	7507	9	0	0
T160	3328	13	0	0
T168	11130	49	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1162	0	0
T82	4851	18	0	0
T87	11062	67	0	0
T93	5206	14	0	0
T122	20649	32	0	0
T155	73031	216	0	0
T156	8751	13	0	0
T157	3239	12	0	0
T158	7507	22	0	0
T160	3328	8	0	0
T168	11130	40	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1225	0	0
T82	4851	15	0	0
T87	11062	51	0	0
T93	5206	4	0	0
T122	20649	41	0	0
T155	73031	254	0	0
T156	8751	16	0	0
T157	3239	13	0	0
T158	7507	11	0	0
T160	3328	5	0	0
T168	11130	46	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1068	0	0
T82	4851	15	0	0
T87	11062	51	0	0
T93	5206	13	0	0
T122	20649	27	0	0
T155	73031	220	0	0
T156	8751	20	0	0
T157	3239	8	0	0
T158	7507	19	0	0
T160	3328	3	0	0
T168	11130	42	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1241	0	0
T82	4851	35	0	0
T87	11062	63	0	0
T93	5206	13	0	0
T122	20649	48	0	0
T155	73031	217	0	0
T156	8751	20	0	0
T157	3239	4	0	0
T158	7507	17	0	0
T160	3328	8	0	0
T168	11130	42	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1144	0	0
T82	4851	13	0	0
T87	11062	48	0	0
T93	5206	9	0	0
T122	20649	49	0	0
T155	73031	235	0	0
T156	8751	3	0	0
T157	3239	4	0	0
T158	7507	4	0	0
T160	3328	14	0	0
T168	11130	52	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1171	0	0
T82	4851	21	0	0
T87	11062	56	0	0
T93	5206	7	0	0
T122	20649	56	0	0
T155	73031	195	0	0
T156	8751	17	0	0
T157	3239	12	0	0
T158	7507	19	0	0
T160	3328	3	0	0
T168	11130	51	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1093	0	0
T82	4851	17	0	0
T87	11062	49	0	0
T93	5206	10	0	0
T122	20649	53	0	0
T155	73031	206	0	0
T156	8751	9	0	0
T157	3239	15	0	0
T158	7507	12	0	0
T160	3328	8	0	0
T167	7444	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1142	0	0
T82	4851	17	0	0
T87	11062	42	0	0
T93	5206	18	0	0
T122	20649	30	0	0
T155	73031	215	0	0
T156	8751	17	0	0
T157	3239	9	0	0
T158	7507	18	0	0
T168	11130	45	0	0
T170	1841	6	0	0