Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167221 |
1 |
|
|
T2 |
1328 |
|
T3 |
3833 |
|
T7 |
262 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92908 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
52076 |
1 |
|
|
T2 |
28 |
|
T3 |
114 |
|
T7 |
258 |
seven_bytes |
3200 |
1 |
|
|
T2 |
55 |
|
T3 |
98 |
|
T17 |
21 |
six_bytes |
3225 |
1 |
|
|
T2 |
47 |
|
T3 |
114 |
|
T17 |
21 |
five_bytes |
3260 |
1 |
|
|
T2 |
37 |
|
T3 |
95 |
|
T17 |
29 |
four_bytes |
3173 |
1 |
|
|
T2 |
36 |
|
T3 |
112 |
|
T17 |
32 |
three_bytes |
3159 |
1 |
|
|
T2 |
48 |
|
T3 |
119 |
|
T17 |
38 |
two_bytes |
3108 |
1 |
|
|
T2 |
36 |
|
T3 |
92 |
|
T17 |
26 |
one_byte |
3112 |
1 |
|
|
T2 |
37 |
|
T3 |
98 |
|
T17 |
15 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164177 |
1 |
|
|
T2 |
1310 |
|
T3 |
3787 |
|
T7 |
254 |
auto[1] |
3044 |
1 |
|
|
T2 |
18 |
|
T3 |
46 |
|
T7 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167221 |
1 |
|
|
T2 |
1328 |
|
T3 |
3833 |
|
T7 |
262 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167208 |
1 |
|
|
T2 |
1328 |
|
T3 |
3833 |
|
T7 |
262 |
auto[1] |
13 |
1 |
|
|
T108 |
1 |
|
T9 |
1 |
|
T14 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1035 |
1 |
|
|
T2 |
1 |
|
T3 |
6 |
|
T7 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3044 |
1 |
|
|
T2 |
18 |
|
T3 |
46 |
|
T7 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163228 |
1 |
|
|
T2 |
845 |
|
T3 |
1219 |
|
T7 |
266 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
88677 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
53529 |
1 |
|
|
T2 |
19 |
|
T3 |
37 |
|
T7 |
262 |
seven_bytes |
3036 |
1 |
|
|
T2 |
23 |
|
T3 |
31 |
|
T18 |
1 |
six_bytes |
3000 |
1 |
|
|
T2 |
25 |
|
T3 |
34 |
|
T18 |
2 |
five_bytes |
2994 |
1 |
|
|
T2 |
22 |
|
T3 |
31 |
|
T18 |
4 |
four_bytes |
2972 |
1 |
|
|
T2 |
28 |
|
T3 |
32 |
|
T18 |
2 |
three_bytes |
3052 |
1 |
|
|
T2 |
22 |
|
T3 |
37 |
|
T18 |
1 |
two_bytes |
3012 |
1 |
|
|
T2 |
23 |
|
T3 |
32 |
|
T18 |
1 |
one_byte |
2956 |
1 |
|
|
T2 |
23 |
|
T3 |
37 |
|
T18 |
1 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160102 |
1 |
|
|
T2 |
833 |
|
T3 |
1205 |
|
T7 |
258 |
auto[1] |
3126 |
1 |
|
|
T2 |
12 |
|
T3 |
14 |
|
T7 |
8 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163228 |
1 |
|
|
T2 |
845 |
|
T3 |
1219 |
|
T7 |
266 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163219 |
1 |
|
|
T2 |
845 |
|
T3 |
1219 |
|
T7 |
266 |
auto[1] |
9 |
1 |
|
|
T9 |
2 |
|
T15 |
1 |
|
T182 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1041 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T7 |
4 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3126 |
1 |
|
|
T2 |
12 |
|
T3 |
14 |
|
T7 |
8 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338317 |
1 |
|
|
T2 |
2737 |
|
T3 |
3996 |
|
T7 |
614 |
auto[1] |
463 |
1 |
|
|
T5 |
45 |
|
T8 |
3 |
|
T9 |
71 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
190768 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
102669 |
1 |
|
|
T2 |
70 |
|
T3 |
120 |
|
T7 |
604 |
seven_bytes |
6501 |
1 |
|
|
T2 |
77 |
|
T3 |
106 |
|
T18 |
15 |
six_bytes |
6462 |
1 |
|
|
T2 |
67 |
|
T3 |
106 |
|
T18 |
10 |
five_bytes |
6562 |
1 |
|
|
T2 |
64 |
|
T3 |
96 |
|
T18 |
13 |
four_bytes |
6500 |
1 |
|
|
T2 |
64 |
|
T3 |
95 |
|
T18 |
10 |
three_bytes |
6467 |
1 |
|
|
T2 |
80 |
|
T3 |
116 |
|
T18 |
11 |
two_bytes |
6448 |
1 |
|
|
T2 |
68 |
|
T3 |
122 |
|
T18 |
12 |
one_byte |
6403 |
1 |
|
|
T2 |
77 |
|
T3 |
109 |
|
T18 |
20 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332598 |
1 |
|
|
T2 |
2703 |
|
T3 |
3940 |
|
T7 |
594 |
auto[1] |
6182 |
1 |
|
|
T2 |
34 |
|
T3 |
56 |
|
T7 |
20 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338780 |
1 |
|
|
T2 |
2737 |
|
T3 |
3996 |
|
T7 |
614 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
338765 |
1 |
|
|
T2 |
2737 |
|
T3 |
3996 |
|
T7 |
614 |
auto[1] |
15 |
1 |
|
|
T109 |
1 |
|
T48 |
1 |
|
T177 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2035 |
1 |
|
|
T2 |
5 |
|
T3 |
7 |
|
T7 |
10 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6182 |
1 |
|
|
T2 |
34 |
|
T3 |
56 |
|
T7 |
20 |