Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257133370	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182166802

1

T1

793410

T2

62460

T3

55869

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	227615286	1			T1	103717		T2	69584		T3	62264
values[0x0]	101758519	1			T1	448306		T2	16058		T3	14847
values[0x1]	109926367	1			T1	484804		T2	17354		T3	15877

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199951305	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

239348867

1

T1

105494

T2

71897

T3

64704

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1282795	1			T1	7518		T2	410		T3	375
valid_sources[0x01]	3722785	1			T1	7805		T2	388		T3	367
valid_sources[0x02]	1738140	1			T1	7983		T2	376		T3	344
valid_sources[0x03]	1286975	1			T1	8034		T2	359		T3	362
valid_sources[0x04]	1432239	1			T1	7564		T2	398		T3	371
valid_sources[0x05]	2444964	1			T1	7692		T2	476		T3	378
valid_sources[0x06]	1290820	1			T1	7608		T2	441		T3	389
valid_sources[0x07]	2174768	1			T1	7922		T2	359		T3	376
valid_sources[0x08]	1314248	1			T1	7445		T2	427		T3	342
valid_sources[0x09]	1294823	1			T1	7731		T2	446		T3	356
valid_sources[0x0a]	1280999	1			T1	7192		T2	398		T3	366
valid_sources[0x0b]	3263517	1			T1	7888		T2	388		T3	327
valid_sources[0x0c]	1290172	1			T1	7836		T2	387		T3	358
valid_sources[0x0d]	1287504	1			T1	7953		T2	365		T3	330
valid_sources[0x0e]	1286817	1			T1	7341		T2	387		T3	341
valid_sources[0x0f]	2155809	1			T1	8071		T2	340		T3	314
valid_sources[0x10]	1278514	1			T1	7740		T2	439		T3	343
valid_sources[0x11]	1287859	1			T1	7709		T2	431		T3	355
valid_sources[0x12]	3255296	1			T1	7856		T2	372		T3	371
valid_sources[0x13]	1286715	1			T1	7795		T2	463		T3	357
valid_sources[0x14]	2198000	1			T1	7649		T2	445		T3	353
valid_sources[0x15]	1288033	1			T1	8286		T2	420		T3	377
valid_sources[0x16]	1283636	1			T1	7539		T2	405		T3	394
valid_sources[0x17]	2091470	1			T1	7654		T2	420		T3	378
valid_sources[0x18]	1302023	1			T1	7691		T2	378		T3	376
valid_sources[0x19]	1288759	1			T1	7731		T2	322		T3	344
valid_sources[0x1a]	1753454	1			T1	7343		T2	420		T3	387
valid_sources[0x1b]	1286794	1			T1	7773		T2	419		T3	344
valid_sources[0x1c]	1386689	1			T1	7616		T2	423		T3	344
valid_sources[0x1d]	2158900	1			T1	7770		T2	407		T3	355
valid_sources[0x1e]	1282310	1			T1	7553		T2	418		T3	377
valid_sources[0x1f]	2210790	1			T1	7753		T2	418		T3	333
valid_sources[0x20]	1957995	1			T1	7431		T2	370		T3	349
valid_sources[0x21]	2211842	1			T1	7577		T2	387		T3	360
valid_sources[0x22]	1320557	1			T1	7698		T2	394		T3	364
valid_sources[0x23]	1438071	1			T1	7750		T2	420		T3	350
valid_sources[0x24]	1421183	1			T1	7716		T2	381		T3	355
valid_sources[0x25]	1283912	1			T1	7438		T2	415		T3	340
valid_sources[0x26]	1283158	1			T1	7735		T2	441		T3	346
valid_sources[0x27]	1279885	1			T1	7311		T2	377		T3	342
valid_sources[0x28]	1379334	1			T1	7623		T2	455		T3	360
valid_sources[0x29]	1321058	1			T1	7714		T2	352		T3	343
valid_sources[0x2a]	1287701	1			T1	8037		T2	357		T3	354
valid_sources[0x2b]	1311286	1			T1	7504		T2	433		T3	348
valid_sources[0x2c]	2083439	1			T1	7791		T2	449		T3	393
valid_sources[0x2d]	3258994	1			T1	7615		T2	379		T3	383
valid_sources[0x2e]	1293306	1			T1	7971		T2	412		T3	357
valid_sources[0x2f]	1291309	1			T1	7701		T2	384		T3	340
valid_sources[0x30]	1288613	1			T1	7560		T2	400		T3	352
valid_sources[0x31]	1288516	1			T1	7937		T2	399		T3	337
valid_sources[0x32]	1282886	1			T1	7708		T2	384		T3	357
valid_sources[0x33]	1292173	1			T1	7896		T2	353		T3	347
valid_sources[0x34]	1286346	1			T1	8032		T2	410		T3	368
valid_sources[0x35]	1280910	1			T1	7777		T2	399		T3	398
valid_sources[0x36]	1292178	1			T1	7652		T2	456		T3	318
valid_sources[0x37]	1280880	1			T1	7651		T2	397		T3	377
valid_sources[0x38]	1934588	1			T1	7580		T2	410		T3	409
valid_sources[0x39]	3796480	1			T1	7452		T2	409		T3	381
valid_sources[0x3a]	1370910	1			T1	8003		T2	436		T3	389
valid_sources[0x3b]	1325035	1			T1	7900		T2	415		T3	355
valid_sources[0x3c]	1286851	1			T1	7545		T2	406		T3	378
valid_sources[0x3d]	1288183	1			T1	7731		T2	355		T3	351
valid_sources[0x3e]	4491969	1			T1	7488		T2	441		T3	365
valid_sources[0x3f]	1324187	1			T1	7898		T2	370		T3	408
valid_sources[0x40]	1289338	1			T1	7748		T2	392		T3	370
valid_sources[0x41]	1287937	1			T1	7620		T2	414		T3	366
valid_sources[0x42]	1284209	1			T1	7872		T2	416		T3	391
valid_sources[0x43]	3599283	1			T1	7706		T2	413		T3	353
valid_sources[0x44]	1395518	1			T1	7663		T2	367		T3	333
valid_sources[0x45]	1412299	1			T1	7626		T2	424		T3	355
valid_sources[0x46]	1355842	1			T1	7882		T2	446		T3	376
valid_sources[0x47]	1317200	1			T1	7909		T2	389		T3	389
valid_sources[0x48]	2133034	1			T1	7665		T2	434		T3	379
valid_sources[0x49]	1278396	1			T1	7091		T2	397		T3	409
valid_sources[0x4a]	1288957	1			T1	7817		T2	403		T3	329
valid_sources[0x4b]	1287340	1			T1	7899		T2	425		T3	393
valid_sources[0x4c]	1315941	1			T1	7517		T2	400		T3	390
valid_sources[0x4d]	1281794	1			T1	7490		T2	400		T3	356
valid_sources[0x4e]	1297041	1			T1	7955		T2	443		T3	343
valid_sources[0x4f]	1293871	1			T1	7865		T2	390		T3	371
valid_sources[0x50]	1285651	1			T1	7551		T2	383		T3	399
valid_sources[0x51]	1290891	1			T1	7313		T2	403		T3	328
valid_sources[0x52]	1283165	1			T1	7759		T2	383		T3	362
valid_sources[0x53]	1276295	1			T1	7928		T2	324		T3	372
valid_sources[0x54]	1932505	1			T1	7213		T2	469		T3	337
valid_sources[0x55]	1289401	1			T1	7836		T2	403		T3	366
valid_sources[0x56]	3769391	1			T1	7291		T2	397		T3	367
valid_sources[0x57]	1479171	1			T1	7604		T2	371		T3	367
valid_sources[0x58]	1305261	1			T1	7690		T2	425		T3	395
valid_sources[0x59]	1444811	1			T1	7991		T2	412		T3	361
valid_sources[0x5a]	1304716	1			T1	7893		T2	410		T3	360
valid_sources[0x5b]	1289960	1			T1	7356		T2	397		T3	376
valid_sources[0x5c]	4236586	1			T1	7543		T2	386		T3	368
valid_sources[0x5d]	3895210	1			T1	7746		T2	395		T3	344
valid_sources[0x5e]	1278375	1			T1	7635		T2	402		T3	393
valid_sources[0x5f]	2138562	1			T1	7614		T2	457		T3	373
valid_sources[0x60]	1285241	1			T1	7928		T2	396		T3	364
valid_sources[0x61]	1362748	1			T1	7647		T2	340		T3	389
valid_sources[0x62]	1287055	1			T1	7676		T2	462		T3	352
valid_sources[0x63]	1306182	1			T1	7382		T2	381		T3	386
valid_sources[0x64]	1302075	1			T1	7526		T2	385		T3	353
valid_sources[0x65]	1288627	1			T1	7465		T2	358		T3	393
valid_sources[0x66]	2174109	1			T1	7535		T2	422		T3	396
valid_sources[0x67]	1280496	1			T1	7633		T2	402		T3	340
valid_sources[0x68]	1320804	1			T1	7725		T2	424		T3	353
valid_sources[0x69]	1284177	1			T1	7596		T2	383		T3	391
valid_sources[0x6a]	1283965	1			T1	7941		T2	434		T3	367
valid_sources[0x6b]	1950251	1			T1	7497		T2	401		T3	329
valid_sources[0x6c]	1449384	1			T1	7276		T2	427		T3	357
valid_sources[0x6d]	1308513	1			T1	7406		T2	405		T3	370
valid_sources[0x6e]	1282686	1			T1	7451		T2	382		T3	385
valid_sources[0x6f]	1285128	1			T1	7712		T2	386		T3	382
valid_sources[0x70]	1289959	1			T1	7530		T2	414		T3	345
valid_sources[0x71]	1748397	1			T1	7511		T2	421		T3	344
valid_sources[0x72]	1315194	1			T1	7575		T2	383		T3	361
valid_sources[0x73]	1285614	1			T1	7870		T2	462		T3	354
valid_sources[0x74]	1288366	1			T1	7768		T2	405		T3	346
valid_sources[0x75]	1495327	1			T1	7653		T2	387		T3	341
valid_sources[0x76]	2312978	1			T1	7595		T2	406		T3	377
valid_sources[0x77]	1288444	1			T1	7471		T2	433		T3	339
valid_sources[0x78]	1557691	1			T1	7673		T2	387		T3	340
valid_sources[0x79]	1302793	1			T1	7668		T2	364		T3	381
valid_sources[0x7a]	1288484	1			T1	7890		T2	398		T3	345
valid_sources[0x7b]	1292978	1			T1	8253		T2	393		T3	368
valid_sources[0x7c]	3597729	1			T1	7377		T2	447		T3	359
valid_sources[0x7d]	1292547	1			T1	8001		T2	391		T3	387
valid_sources[0x7e]	1286875	1			T1	7857		T2	403		T3	343
valid_sources[0x7f]	3284401	1			T1	7710		T2	429		T3	366
valid_sources[0x80]	1280543	1			T1	7931		T2	394		T3	374

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70431274

1

T1

323643

T2

43383

T3

38267

values[0x0]

all_enables

biggest_size

60057504

1

T1

255347

T2

10056

T3

9369

values[0x1]

all_enables

biggest_size

51678024

1

T1

214420

T2

9021

T3

8233