Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

257553156

1

T1

117687

T2

40536

T3

37119

full_word

182193045

1

T1

793410

T2

62460

T3

55869

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439745921	1			T1	197028		T2	102996		T3	92988
auto[TlIntgErrCmd]	87	1			T128	3		T129	8		T130	7
auto[TlIntgErrData]	101	1			T128	3		T129	8		T130	8
auto[TlIntgErrBoth]	92	1			T128	4		T129	4		T130	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227699189

1

T1

103717

T2

69584

T3

62264

auto[1]

212047012

1

T1

933110

T2

33412

T3

30724

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157261118	1			T1	713532		T2	26201		T3	23997
auto[TlIntgErrNone]	partial	auto[1]	100291776	1			T1	463343		T2	14335		T3	13122
auto[TlIntgErrNone]	full_word	auto[0]	70437946	1			T1	323643		T2	43383		T3	38267
auto[TlIntgErrNone]	full_word	auto[1]	111755081	1			T1	469767		T2	19077		T3	17602
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T129	2		T130	3		T170	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T128	3		T129	4		T130	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T129	1		T170	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T129	1		T130	2		T186	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T128	1		T129	6		T130	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T128	2		T129	1		T130	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T129	1		T187	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T189	1		T190	1		T184	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T128	1		T129	3		T130	4
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T128	3		T129	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T185	1		T188	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T187	1		-	-		-	-