Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	96729	0	0
entropy_period_rd_A	2147483647	1490	0	0
intr_enable_rd_A	2147483647	2237	0	0
prefix_0_rd_A	2147483647	1598	0	0
prefix_10_rd_A	2147483647	1635	0	0
prefix_1_rd_A	2147483647	1579	0	0
prefix_2_rd_A	2147483647	1603	0	0
prefix_3_rd_A	2147483647	1615	0	0
prefix_4_rd_A	2147483647	1571	0	0
prefix_5_rd_A	2147483647	1635	0	0
prefix_6_rd_A	2147483647	1656	0	0
prefix_7_rd_A	2147483647	1600	0	0
prefix_8_rd_A	2147483647	1611	0	0
prefix_9_rd_A	2147483647	1487	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	96729	0	0
T61	626050	10056	0	0
T62	0	65917	0	0
T63	0	17518	0	0
T130	0	1	0	0
T134	0	2	0	0
T135	0	103	0	0
T136	0	1	0	0
T137	0	23	0	0
T139	0	5	0	0
T140	210850	0	0	0
T141	54784	0	0	0
T142	183941	0	0	0
T143	116150	0	0	0
T144	170237	0	0	0
T145	69388	0	0	0
T146	265042	0	0	0
T147	2085	0	0	0
T148	77587	0	0	0
T149	0	23	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490	0	0
T98	5214	15	0	0
T100	8398	45	0	0
T101	3684	4	0	0
T103	3112	9	0	0
T105	5867	36	0	0
T136	4426	12	0	0
T168	24518	221	0	0
T169	10647	41	0	0
T170	11220	38	0	0
T171	7624	49	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T98	5214	18	0	0
T100	8398	40	0	0
T131	2402	4	0	0
T133	1541	12	0	0
T136	4426	10	0	0
T168	24518	221	0	0
T169	10647	31	0	0
T170	11220	39	0	0
T172	1336	10	0	0
T173	846	3	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1598	0	0
T98	5214	10	0	0
T100	8398	40	0	0
T101	3684	14	0	0
T103	3112	14	0	0
T105	5867	19	0	0
T136	4426	7	0	0
T168	24518	230	0	0
T169	10647	22	0	0
T170	11220	31	0	0
T171	7624	36	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T98	5214	11	0	0
T100	8398	34	0	0
T105	5867	14	0	0
T136	4426	8	0	0
T168	24518	200	0	0
T169	10647	64	0	0
T170	11220	8	0	0
T171	7624	22	0	0
T174	144047	446	0	0
T175	10936	37	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T98	5214	15	0	0
T100	8398	15	0	0
T101	3684	14	0	0
T105	5867	16	0	0
T136	4426	6	0	0
T168	24518	234	0	0
T169	10647	42	0	0
T170	11220	17	0	0
T171	7624	37	0	0
T174	144047	472	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T98	5214	21	0	0
T100	8398	28	0	0
T101	3684	14	0	0
T103	3112	3	0	0
T105	5867	21	0	0
T136	4426	8	0	0
T168	24518	213	0	0
T169	10647	49	0	0
T170	11220	29	0	0
T171	7624	25	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1615	0	0
T98	5214	11	0	0
T100	8398	21	0	0
T101	3684	15	0	0
T103	3112	9	0	0
T105	5867	10	0	0
T136	4426	11	0	0
T168	24518	208	0	0
T169	10647	70	0	0
T170	11220	21	0	0
T171	7624	29	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1571	0	0
T98	5214	14	0	0
T100	8398	22	0	0
T101	3684	21	0	0
T103	3112	3	0	0
T105	5867	20	0	0
T136	4426	8	0	0
T168	24518	181	0	0
T169	10647	40	0	0
T170	11220	16	0	0
T171	7624	41	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T98	5214	14	0	0
T100	8398	27	0	0
T101	3684	17	0	0
T105	5867	23	0	0
T136	4426	3	0	0
T168	24518	247	0	0
T169	10647	25	0	0
T170	11220	17	0	0
T171	7624	38	0	0
T174	144047	438	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1656	0	0
T98	5214	4	0	0
T100	8398	26	0	0
T101	3684	6	0	0
T103	3112	11	0	0
T105	5867	13	0	0
T136	4426	7	0	0
T168	24518	206	0	0
T169	10647	52	0	0
T170	11220	28	0	0
T171	7624	31	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1600	0	0
T98	5214	9	0	0
T100	8398	34	0	0
T101	3684	3	0	0
T103	3112	5	0	0
T105	5867	19	0	0
T136	4426	16	0	0
T168	24518	232	0	0
T169	10647	73	0	0
T170	11220	16	0	0
T171	7624	34	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1611	0	0
T98	5214	18	0	0
T100	8398	26	0	0
T101	3684	19	0	0
T103	3112	5	0	0
T105	5867	18	0	0
T136	4426	9	0	0
T168	24518	237	0	0
T169	10647	30	0	0
T170	11220	19	0	0
T171	7624	28	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1487	0	0
T98	5214	18	0	0
T100	8398	28	0	0
T101	3684	19	0	0
T105	5867	29	0	0
T136	4426	10	0	0
T168	24518	239	0	0
T169	10647	5	0	0
T170	11220	23	0	0
T171	7624	39	0	0
T174	144047	428	0	0