Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255870011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

181962843

1

T1

88328

T2

791483

T3

208494

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	226844535	1			T1	119368		T2	106072		T3	269791
values[0x0]	101394697	1			T1	24545		T2	455752		T3	118301
values[0x1]	109593622	1			T1	25880		T2	500843		T3	128188

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	198865219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

238967635

1

T1

108995

T2

106793

T3

276942

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1319042	1			T1	633		T2	7858		T3	1986
valid_sources[0x01]	1340454	1			T1	611		T2	7858		T3	2026
valid_sources[0x02]	1315844	1			T1	649		T2	7834		T3	2099
valid_sources[0x03]	1347827	1			T1	686		T2	7997		T3	1892
valid_sources[0x04]	1980514	1			T1	640		T2	7774		T3	2085
valid_sources[0x05]	1317602	1			T1	685		T2	7881		T3	2014
valid_sources[0x06]	1316620	1			T1	646		T2	7916		T3	2012
valid_sources[0x07]	1314890	1			T1	685		T2	7935		T3	2078
valid_sources[0x08]	1401827	1			T1	678		T2	7748		T3	1989
valid_sources[0x09]	1783769	1			T1	621		T2	7961		T3	1970
valid_sources[0x0a]	2712707	1			T1	621		T2	7940		T3	2157
valid_sources[0x0b]	2161488	1			T1	652		T2	7984		T3	1938
valid_sources[0x0c]	3282618	1			T1	669		T2	8059		T3	1966
valid_sources[0x0d]	1756741	1			T1	673		T2	7800		T3	2056
valid_sources[0x0e]	1540604	1			T1	665		T2	7897		T3	1994
valid_sources[0x0f]	1308923	1			T1	649		T2	7932		T3	2128
valid_sources[0x10]	2235599	1			T1	685		T2	7720		T3	2011
valid_sources[0x11]	1315644	1			T1	654		T2	7769		T3	2033
valid_sources[0x12]	1328983	1			T1	633		T2	7895		T3	1970
valid_sources[0x13]	2284347	1			T1	675		T2	7868		T3	1907
valid_sources[0x14]	1316747	1			T1	663		T2	8013		T3	1787
valid_sources[0x15]	1312033	1			T1	614		T2	7771		T3	1928
valid_sources[0x16]	2180774	1			T1	677		T2	7774		T3	2061
valid_sources[0x17]	2219818	1			T1	673		T2	7747		T3	2092
valid_sources[0x18]	1308551	1			T1	684		T2	7926		T3	2028
valid_sources[0x19]	2449411	1			T1	663		T2	7929		T3	2109
valid_sources[0x1a]	1321232	1			T1	659		T2	7788		T3	1965
valid_sources[0x1b]	1313383	1			T1	683		T2	7878		T3	1899
valid_sources[0x1c]	1804509	1			T1	625		T2	7785		T3	1978
valid_sources[0x1d]	1351905	1			T1	627		T2	7998		T3	2023
valid_sources[0x1e]	3286570	1			T1	685		T2	7698		T3	1989
valid_sources[0x1f]	1422964	1			T1	654		T2	7747		T3	2081
valid_sources[0x20]	1734307	1			T1	649		T2	8015		T3	2074
valid_sources[0x21]	2282158	1			T1	664		T2	7975		T3	2113
valid_sources[0x22]	1311888	1			T1	641		T2	7984		T3	2103
valid_sources[0x23]	1372402	1			T1	675		T2	8078		T3	2042
valid_sources[0x24]	4061784	1			T1	665		T2	7825		T3	1971
valid_sources[0x25]	1955465	1			T1	666		T2	7849		T3	1887
valid_sources[0x26]	2163303	1			T1	647		T2	8053		T3	2019
valid_sources[0x27]	1308305	1			T1	693		T2	7995		T3	1977
valid_sources[0x28]	1315873	1			T1	636		T2	7901		T3	2019
valid_sources[0x29]	2242572	1			T1	646		T2	7808		T3	1979
valid_sources[0x2a]	1309722	1			T1	697		T2	7951		T3	2010
valid_sources[0x2b]	1376798	1			T1	650		T2	7925		T3	1984
valid_sources[0x2c]	1311458	1			T1	658		T2	7863		T3	1988
valid_sources[0x2d]	1314534	1			T1	685		T2	7985		T3	2064
valid_sources[0x2e]	2178650	1			T1	661		T2	7884		T3	1900
valid_sources[0x2f]	3350800	1			T1	720		T2	7806		T3	2074
valid_sources[0x30]	1985057	1			T1	676		T2	7788		T3	2054
valid_sources[0x31]	1316930	1			T1	615		T2	7906		T3	2075
valid_sources[0x32]	1455751	1			T1	694		T2	7869		T3	1990
valid_sources[0x33]	1416226	1			T1	612		T2	7950		T3	1931
valid_sources[0x34]	1372032	1			T1	672		T2	7870		T3	1939
valid_sources[0x35]	1330931	1			T1	695		T2	7663		T3	2024
valid_sources[0x36]	2201359	1			T1	633		T2	7744		T3	2115
valid_sources[0x37]	1983953	1			T1	676		T2	7870		T3	1929
valid_sources[0x38]	3315861	1			T1	740		T2	7885		T3	2055
valid_sources[0x39]	2226319	1			T1	649		T2	8033		T3	2014
valid_sources[0x3a]	2239568	1			T1	625		T2	8140		T3	1933
valid_sources[0x3b]	1316244	1			T1	670		T2	7933		T3	2065
valid_sources[0x3c]	1510118	1			T1	628		T2	7943		T3	2155
valid_sources[0x3d]	1319460	1			T1	654		T2	7953		T3	1950
valid_sources[0x3e]	2409126	1			T1	616		T2	7841		T3	2175
valid_sources[0x3f]	1319422	1			T1	635		T2	7877		T3	2097
valid_sources[0x40]	3028958	1			T1	675		T2	7725		T3	2038
valid_sources[0x41]	1317903	1			T1	658		T2	7928		T3	2004
valid_sources[0x42]	1412121	1			T1	681		T2	7901		T3	2003
valid_sources[0x43]	1318329	1			T1	662		T2	7658		T3	2090
valid_sources[0x44]	1701952	1			T1	671		T2	7719		T3	2148
valid_sources[0x45]	1311498	1			T1	651		T2	7887		T3	1808
valid_sources[0x46]	1311289	1			T1	690		T2	8004		T3	1968
valid_sources[0x47]	1336452	1			T1	679		T2	7891		T3	2011
valid_sources[0x48]	2210846	1			T1	703		T2	7871		T3	2011
valid_sources[0x49]	1314913	1			T1	664		T2	7940		T3	2069
valid_sources[0x4a]	2187103	1			T1	631		T2	7887		T3	2012
valid_sources[0x4b]	1421866	1			T1	689		T2	7877		T3	1906
valid_sources[0x4c]	1341201	1			T1	654		T2	7916		T3	2033
valid_sources[0x4d]	1353926	1			T1	653		T2	7832		T3	1874
valid_sources[0x4e]	1373551	1			T1	656		T2	7982		T3	2062
valid_sources[0x4f]	1631756	1			T1	718		T2	7898		T3	2103
valid_sources[0x50]	1985218	1			T1	640		T2	7969		T3	2058
valid_sources[0x51]	1310028	1			T1	669		T2	7854		T3	1991
valid_sources[0x52]	1405883	1			T1	667		T2	7936		T3	2136
valid_sources[0x53]	1341244	1			T1	701		T2	7895		T3	2022
valid_sources[0x54]	1312309	1			T1	649		T2	7789		T3	1951
valid_sources[0x55]	1317031	1			T1	662		T2	7832		T3	1937
valid_sources[0x56]	1310924	1			T1	685		T2	7935		T3	2171
valid_sources[0x57]	1316246	1			T1	671		T2	7623		T3	1983
valid_sources[0x58]	1365472	1			T1	693		T2	7780		T3	2095
valid_sources[0x59]	1316033	1			T1	642		T2	7919		T3	1972
valid_sources[0x5a]	1407786	1			T1	675		T2	8126		T3	1951
valid_sources[0x5b]	1444411	1			T1	684		T2	7845		T3	1920
valid_sources[0x5c]	1311523	1			T1	643		T2	7893		T3	2074
valid_sources[0x5d]	1432330	1			T1	672		T2	7812		T3	1906
valid_sources[0x5e]	2169967	1			T1	684		T2	8053		T3	1989
valid_sources[0x5f]	1314243	1			T1	626		T2	7813		T3	2163
valid_sources[0x60]	2294400	1			T1	631		T2	7703		T3	2010
valid_sources[0x61]	2032523	1			T1	678		T2	7927		T3	2091
valid_sources[0x62]	1337841	1			T1	645		T2	7789		T3	1973
valid_sources[0x63]	2244065	1			T1	689		T2	7931		T3	2008
valid_sources[0x64]	1309806	1			T1	660		T2	7825		T3	2004
valid_sources[0x65]	1315566	1			T1	679		T2	7945		T3	2080
valid_sources[0x66]	1944005	1			T1	611		T2	7861		T3	2054
valid_sources[0x67]	1325564	1			T1	674		T2	7928		T3	1940
valid_sources[0x68]	1981074	1			T1	640		T2	7855		T3	2040
valid_sources[0x69]	2224506	1			T1	688		T2	8042		T3	2034
valid_sources[0x6a]	3283808	1			T1	639		T2	7834		T3	2039
valid_sources[0x6b]	1313738	1			T1	679		T2	7987		T3	2037
valid_sources[0x6c]	2235855	1			T1	682		T2	7834		T3	2070
valid_sources[0x6d]	1313148	1			T1	671		T2	8015		T3	2051
valid_sources[0x6e]	1317588	1			T1	623		T2	8053		T3	2051
valid_sources[0x6f]	1782168	1			T1	691		T2	7875		T3	1990
valid_sources[0x70]	1319066	1			T1	648		T2	7992		T3	2028
valid_sources[0x71]	1465374	1			T1	608		T2	7973		T3	2038
valid_sources[0x72]	1316178	1			T1	708		T2	7973		T3	1918
valid_sources[0x73]	2152250	1			T1	676		T2	7821		T3	2119
valid_sources[0x74]	1320213	1			T1	677		T2	7743		T3	2040
valid_sources[0x75]	2326774	1			T1	680		T2	7872		T3	2097
valid_sources[0x76]	1416928	1			T1	678		T2	7963		T3	1920
valid_sources[0x77]	1318432	1			T1	665		T2	7853		T3	2045
valid_sources[0x78]	1483694	1			T1	649		T2	7894		T3	1909
valid_sources[0x79]	1317926	1			T1	660		T2	7991		T3	2014
valid_sources[0x7a]	1331092	1			T1	654		T2	7807		T3	2042
valid_sources[0x7b]	2239436	1			T1	674		T2	7941		T3	1901
valid_sources[0x7c]	1315864	1			T1	696		T2	7802		T3	1991
valid_sources[0x7d]	3610463	1			T1	679		T2	8010		T3	2063
valid_sources[0x7e]	3316012	1			T1	659		T2	7928		T3	1993
valid_sources[0x7f]	1311711	1			T1	634		T2	7890		T3	1977
valid_sources[0x80]	1762241	1			T1	665		T2	7787		T3	1986

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70338314

1

T1

59588

T2

329586

T3

85087

values[0x0]

all_enables

biggest_size

59976737

1

T1

15441

T2

251211

T3

67070

values[0x1]

all_enables

biggest_size

51647792

1

T1

13299

T2

210686

T3

56337