Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

256976584

1

T1

81465

T2

122584

T3

307786

full_word

182033104

1

T1

88328

T2

791483

T3

208494

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	439009368	1			T1	169793		T2	201732		T3	516280
auto[TlIntgErrCmd]	113	1			T138	8		T139	4		T140	8
auto[TlIntgErrData]	102	1			T138	4		T139	3		T140	4
auto[TlIntgErrBoth]	105	1			T138	8		T139	3		T140	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227059400

1

T1

119368

T2

106072

T3

269791

auto[1]

211950288

1

T1

50425

T2

956595

T3

246489

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	156703152	1			T1	59780		T2	731143		T3	184704
auto[TlIntgErrNone]	partial	auto[1]	100273135	1			T1	21685		T2	494698		T3	123082
auto[TlIntgErrNone]	full_word	auto[0]	70356094	1			T1	59588		T2	329586		T3	85087
auto[TlIntgErrNone]	full_word	auto[1]	111676987	1			T1	28740		T2	461897		T3	123407
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T138	6		T139	1		T140	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T138	2		T139	3		T140	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T158	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T140	1		T158	1		T194	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T138	2		T139	2		T140	1
auto[TlIntgErrData]	partial	auto[1]	36	1			T139	1		T140	2		T160	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T138	1		T140	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T138	1		T158	1		T195	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T138	3		T139	1		T140	4
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T138	5		T139	2		T140	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T192	1		T196	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T195	1		T197	1		T192	1