Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	258659	0	0
entropy_period_rd_A	2147483647	1606	0	0
intr_enable_rd_A	2147483647	2205	0	0
prefix_0_rd_A	2147483647	1408	0	0
prefix_10_rd_A	2147483647	1369	0	0
prefix_1_rd_A	2147483647	1392	0	0
prefix_2_rd_A	2147483647	1421	0	0
prefix_3_rd_A	2147483647	1517	0	0
prefix_4_rd_A	2147483647	1355	0	0
prefix_5_rd_A	2147483647	1485	0	0
prefix_6_rd_A	2147483647	1426	0	0
prefix_7_rd_A	2147483647	1359	0	0
prefix_8_rd_A	2147483647	1459	0	0
prefix_9_rd_A	2147483647	1510	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258659	0	0
T68	648115	91955	0	0
T69	0	144817	0	0
T70	0	18295	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	2	0	0
T145	0	174	0	0
T146	0	2	0	0
T147	0	257	0	0
T148	0	261	0	0
T149	101738	0	0	0
T150	526099	0	0	0
T151	607431	0	0	0
T152	18612	0	0	0
T153	221772	0	0	0
T154	147682	0	0	0
T155	175203	0	0	0
T156	846236	0	0	0
T157	624148	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T97	2964	6	0	0
T146	4169	5	0	0
T158	23785	124	0	0
T167	3037	13	0	0
T168	11181	54	0	0
T169	1730	2	0	0
T170	1868	7	0	0
T171	5902	8	0	0
T172	7511	5	0	0
T173	8120	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2205	0	0
T146	4169	1	0	0
T158	23785	183	0	0
T167	3037	25	0	0
T168	11181	46	0	0
T169	1730	18	0	0
T170	1868	8	0	0
T171	5902	12	0	0
T174	1238	23	0	0
T175	1267	16	0	0
T176	1444	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408	0	0
T97	2964	9	0	0
T146	4169	11	0	0
T158	23785	72	0	0
T167	3037	6	0	0
T168	11181	33	0	0
T169	1730	7	0	0
T171	5902	13	0	0
T172	7511	8	0	0
T173	8120	12	0	0
T177	8633	5	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1369	0	0
T97	2964	7	0	0
T158	23785	63	0	0
T167	3037	11	0	0
T168	11181	63	0	0
T169	1730	7	0	0
T170	1868	5	0	0
T171	5902	6	0	0
T172	7511	1	0	0
T173	8120	19	0	0
T177	8633	2	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1392	0	0
T146	4169	16	0	0
T147	14347	2	0	0
T158	23785	76	0	0
T167	3037	10	0	0
T168	11181	5	0	0
T169	1730	9	0	0
T170	1868	4	0	0
T171	5902	2	0	0
T172	7511	4	0	0
T177	8633	7	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T97	2964	13	0	0
T146	4169	15	0	0
T158	23785	88	0	0
T167	3037	7	0	0
T168	11181	24	0	0
T169	1730	1	0	0
T170	1868	4	0	0
T172	7511	8	0	0
T173	8120	20	0	0
T177	8633	20	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1517	0	0
T97	2964	9	0	0
T146	4169	12	0	0
T158	23785	97	0	0
T167	3037	2	0	0
T168	11181	61	0	0
T169	1730	6	0	0
T170	1868	3	0	0
T171	5902	18	0	0
T172	7511	2	0	0
T177	8633	9	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1355	0	0
T97	2964	5	0	0
T146	4169	10	0	0
T158	23785	47	0	0
T167	3037	9	0	0
T168	11181	34	0	0
T169	1730	7	0	0
T171	5902	13	0	0
T172	7511	3	0	0
T173	8120	13	0	0
T177	8633	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1485	0	0
T97	2964	3	0	0
T146	4169	6	0	0
T158	23785	90	0	0
T167	3037	6	0	0
T168	11181	81	0	0
T169	1730	6	0	0
T171	5902	10	0	0
T172	7511	4	0	0
T173	8120	15	0	0
T177	8633	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1426	0	0
T97	2964	5	0	0
T146	4169	10	0	0
T158	23785	68	0	0
T167	3037	12	0	0
T168	11181	46	0	0
T171	5902	26	0	0
T172	7511	20	0	0
T173	8120	21	0	0
T177	8633	24	0	0
T178	8178	36	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1359	0	0
T146	4169	10	0	0
T158	23785	79	0	0
T167	3037	1	0	0
T168	11181	27	0	0
T169	1730	4	0	0
T171	5902	1	0	0
T172	7511	9	0	0
T173	8120	20	0	0
T177	8633	6	0	0
T178	8178	24	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1459	0	0
T97	2964	5	0	0
T146	4169	10	0	0
T158	23785	64	0	0
T167	3037	15	0	0
T168	11181	62	0	0
T169	1730	1	0	0
T171	5902	10	0	0
T172	7511	9	0	0
T177	8633	8	0	0
T179	5107	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1510	0	0
T97	2964	6	0	0
T146	4169	11	0	0
T158	23785	93	0	0
T167	3037	1	0	0
T168	11181	58	0	0
T169	1730	4	0	0
T171	5902	21	0	0
T172	7511	8	0	0
T173	8120	19	0	0
T177	8633	9	0	0