Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172255 |
1 |
|
|
T3 |
318 |
|
T8 |
682 |
|
T9 |
1241 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87109 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
64542 |
1 |
|
|
T3 |
314 |
|
T8 |
672 |
|
T9 |
1225 |
seven_bytes |
2913 |
1 |
|
|
T20 |
34 |
|
T18 |
4 |
|
T15 |
47 |
six_bytes |
2885 |
1 |
|
|
T20 |
33 |
|
T18 |
6 |
|
T15 |
49 |
five_bytes |
3004 |
1 |
|
|
T20 |
45 |
|
T18 |
11 |
|
T15 |
50 |
four_bytes |
2914 |
1 |
|
|
T20 |
30 |
|
T18 |
6 |
|
T15 |
43 |
three_bytes |
2962 |
1 |
|
|
T20 |
43 |
|
T18 |
5 |
|
T15 |
36 |
two_bytes |
2913 |
1 |
|
|
T20 |
41 |
|
T18 |
5 |
|
T15 |
45 |
one_byte |
3013 |
1 |
|
|
T20 |
36 |
|
T18 |
9 |
|
T15 |
55 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168905 |
1 |
|
|
T3 |
310 |
|
T8 |
662 |
|
T9 |
1209 |
auto[1] |
3350 |
1 |
|
|
T3 |
8 |
|
T8 |
20 |
|
T9 |
32 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172255 |
1 |
|
|
T3 |
318 |
|
T8 |
682 |
|
T9 |
1241 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172242 |
1 |
|
|
T3 |
318 |
|
T8 |
682 |
|
T9 |
1241 |
auto[1] |
13 |
1 |
|
|
T179 |
1 |
|
T180 |
1 |
|
T70 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1187 |
1 |
|
|
T3 |
4 |
|
T8 |
10 |
|
T9 |
16 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3350 |
1 |
|
|
T3 |
8 |
|
T8 |
20 |
|
T9 |
32 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
153491 |
1 |
|
|
T3 |
91 |
|
T8 |
720 |
|
T9 |
508 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
77301 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
57863 |
1 |
|
|
T3 |
89 |
|
T8 |
710 |
|
T9 |
501 |
seven_bytes |
2675 |
1 |
|
|
T20 |
42 |
|
T18 |
2 |
|
T15 |
25 |
six_bytes |
2563 |
1 |
|
|
T20 |
45 |
|
T18 |
1 |
|
T15 |
14 |
five_bytes |
2548 |
1 |
|
|
T20 |
34 |
|
T18 |
1 |
|
T15 |
19 |
four_bytes |
2584 |
1 |
|
|
T20 |
44 |
|
T18 |
2 |
|
T15 |
13 |
three_bytes |
2671 |
1 |
|
|
T20 |
41 |
|
T18 |
1 |
|
T15 |
18 |
two_bytes |
2597 |
1 |
|
|
T20 |
40 |
|
T18 |
1 |
|
T15 |
26 |
one_byte |
2689 |
1 |
|
|
T20 |
33 |
|
T15 |
24 |
|
T60 |
24 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
150481 |
1 |
|
|
T3 |
87 |
|
T8 |
700 |
|
T9 |
494 |
auto[1] |
3010 |
1 |
|
|
T3 |
4 |
|
T8 |
20 |
|
T9 |
14 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
153491 |
1 |
|
|
T3 |
91 |
|
T8 |
720 |
|
T9 |
508 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
153481 |
1 |
|
|
T3 |
91 |
|
T8 |
720 |
|
T9 |
508 |
auto[1] |
10 |
1 |
|
|
T16 |
1 |
|
T181 |
1 |
|
T182 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1061 |
1 |
|
|
T3 |
2 |
|
T8 |
10 |
|
T9 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3010 |
1 |
|
|
T3 |
4 |
|
T8 |
20 |
|
T9 |
14 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
321982 |
1 |
|
|
T3 |
98 |
|
T7 |
3 |
|
T8 |
621 |
auto[1] |
551 |
1 |
|
|
T4 |
72 |
|
T10 |
75 |
|
T11 |
82 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
169043 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
113376 |
1 |
|
|
T3 |
97 |
|
T7 |
3 |
|
T8 |
612 |
seven_bytes |
5773 |
1 |
|
|
T20 |
112 |
|
T40 |
10 |
|
T18 |
5 |
six_bytes |
5781 |
1 |
|
|
T20 |
96 |
|
T40 |
1 |
|
T18 |
10 |
five_bytes |
5730 |
1 |
|
|
T20 |
104 |
|
T40 |
6 |
|
T18 |
10 |
four_bytes |
5723 |
1 |
|
|
T20 |
107 |
|
T40 |
6 |
|
T18 |
6 |
three_bytes |
5784 |
1 |
|
|
T20 |
104 |
|
T40 |
7 |
|
T18 |
13 |
two_bytes |
5650 |
1 |
|
|
T20 |
102 |
|
T40 |
4 |
|
T18 |
9 |
one_byte |
5673 |
1 |
|
|
T20 |
110 |
|
T40 |
5 |
|
T18 |
1 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
316261 |
1 |
|
|
T3 |
96 |
|
T7 |
3 |
|
T8 |
603 |
auto[1] |
6272 |
1 |
|
|
T3 |
2 |
|
T8 |
18 |
|
T9 |
44 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322533 |
1 |
|
|
T3 |
98 |
|
T7 |
3 |
|
T8 |
621 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
322508 |
1 |
|
|
T3 |
98 |
|
T7 |
3 |
|
T8 |
621 |
auto[1] |
25 |
1 |
|
|
T20 |
2 |
|
T4 |
1 |
|
T183 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2153 |
1 |
|
|
T3 |
1 |
|
T8 |
9 |
|
T9 |
22 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6272 |
1 |
|
|
T3 |
2 |
|
T8 |
18 |
|
T9 |
44 |