Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260914569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183808841

1

T1

5

T2

910442

T3

4557

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230657435	1			T1	1		T2	118949		T3	6067
values[0x0]	102855237	1			T1	7		T2	553138		T3	1114
values[0x1]	111210738	1			T1	8		T2	602085		T3	1154

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202871747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241851663

1

T1

7

T2

122686

T3

5519

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1370081	1			T3	32		T17	6		T34	9007
valid_sources[0x01]	1405367	1			T3	39		T17	7		T34	9108
valid_sources[0x02]	1343691	1			T3	28		T17	6		T34	9311
valid_sources[0x03]	1532690	1			T3	19		T17	5		T34	8919
valid_sources[0x04]	1354255	1			T3	30		T17	10		T34	9149
valid_sources[0x05]	1345887	1			T3	24		T17	6		T34	9026
valid_sources[0x06]	1500595	1			T3	31		T17	6		T34	9014
valid_sources[0x07]	1347025	1			T3	24		T17	9		T34	8980
valid_sources[0x08]	3745809	1			T3	25		T17	2		T34	9077
valid_sources[0x09]	1345479	1			T3	36		T17	3		T34	8956
valid_sources[0x0a]	2361049	1			T3	39		T17	10		T34	8822
valid_sources[0x0b]	1382245	1			T3	25		T17	5		T34	9131
valid_sources[0x0c]	1456670	1			T3	28		T17	6		T34	9008
valid_sources[0x0d]	1348289	1			T3	25		T17	4		T34	9125
valid_sources[0x0e]	1348395	1			T3	41		T17	6		T34	8901
valid_sources[0x0f]	1434948	1			T3	31		T17	3		T34	8978
valid_sources[0x10]	3682495	1			T3	28		T17	10		T34	9131
valid_sources[0x11]	1341750	1			T3	34		T17	7		T34	8885
valid_sources[0x12]	1350423	1			T3	31		T17	4		T34	9143
valid_sources[0x13]	2200025	1			T3	31		T17	6		T34	9172
valid_sources[0x14]	2241165	1			T3	39		T17	8		T34	9005
valid_sources[0x15]	1338869	1			T3	24		T17	9		T34	9137
valid_sources[0x16]	1348141	1			T3	28		T17	12		T34	9091
valid_sources[0x17]	3290527	1			T3	20		T17	10		T34	9136
valid_sources[0x18]	1346923	1			T3	34		T17	4		T34	9132
valid_sources[0x19]	1439376	1			T3	34		T17	7		T34	8951
valid_sources[0x1a]	2447327	1			T3	38		T17	7		T34	9171
valid_sources[0x1b]	1341301	1			T3	32		T17	4		T34	9112
valid_sources[0x1c]	1993216	1			T3	33		T17	11		T34	9170
valid_sources[0x1d]	2436935	1			T3	30		T17	8		T34	9141
valid_sources[0x1e]	2202271	1			T3	32		T17	7		T34	9080
valid_sources[0x1f]	1801107	1			T3	25		T17	10		T34	8876
valid_sources[0x20]	1339320	1			T3	39		T17	12		T34	9032
valid_sources[0x21]	1347008	1			T3	33		T17	9		T34	9022
valid_sources[0x22]	2769954	1			T3	25		T17	5		T34	9207
valid_sources[0x23]	1796103	1			T3	63		T17	8		T34	9057
valid_sources[0x24]	1395158	1			T3	33		T17	9		T34	8875
valid_sources[0x25]	1472538	1			T3	24		T17	4		T34	9133
valid_sources[0x26]	1346905	1			T3	26		T17	12		T34	9048
valid_sources[0x27]	1335935	1			T3	42		T17	11		T34	8989
valid_sources[0x28]	1350873	1			T3	41		T17	9		T34	9064
valid_sources[0x29]	1523200	1			T3	20		T17	8		T34	9133
valid_sources[0x2a]	1376202	1			T3	49		T17	2		T34	9106
valid_sources[0x2b]	1352719	1			T3	29		T17	11		T34	8994
valid_sources[0x2c]	1345753	1			T3	37		T17	7		T34	9135
valid_sources[0x2d]	1345773	1			T3	33		T17	6		T34	9198
valid_sources[0x2e]	1741207	1			T3	23		T17	4		T34	9037
valid_sources[0x2f]	1351717	1			T3	40		T17	6		T34	8964
valid_sources[0x30]	1543517	1			T3	36		T17	13		T34	9005
valid_sources[0x31]	1814299	1			T3	22		T17	7		T34	8999
valid_sources[0x32]	2884792	1			T3	39		T17	9		T34	9083
valid_sources[0x33]	1347277	1			T3	33		T17	9		T34	9028
valid_sources[0x34]	1426436	1			T3	42		T17	18		T34	9106
valid_sources[0x35]	2250863	1			T3	32		T17	8		T34	9232
valid_sources[0x36]	1502305	1			T3	45		T17	13		T34	9013
valid_sources[0x37]	1342294	1			T3	47		T17	10		T34	8979
valid_sources[0x38]	1345321	1			T3	22		T17	10		T34	9183
valid_sources[0x39]	1339373	1			T3	29		T17	5		T34	9160
valid_sources[0x3a]	3296103	1			T3	35		T17	4		T34	9129
valid_sources[0x3b]	1342934	1			T3	40		T17	8		T34	8980
valid_sources[0x3c]	1358253	1			T3	26		T17	6		T34	9007
valid_sources[0x3d]	1366016	1			T3	23		T17	9		T34	9111
valid_sources[0x3e]	1346385	1			T3	32		T17	10		T34	9111
valid_sources[0x3f]	1345560	1			T3	21		T17	8		T34	9050
valid_sources[0x40]	1343209	1			T3	33		T17	7		T34	9110
valid_sources[0x41]	1345500	1			T3	27		T17	6		T34	9099
valid_sources[0x42]	1801856	1			T3	37		T17	14		T34	8901
valid_sources[0x43]	1350944	1			T3	37		T17	14		T34	9214
valid_sources[0x44]	1345281	1			T3	23		T17	4		T34	9213
valid_sources[0x45]	3320016	1			T3	33		T17	11		T34	9096
valid_sources[0x46]	1760420	1			T3	26		T17	11		T34	9011
valid_sources[0x47]	3638577	1			T3	26		T17	9		T34	9041
valid_sources[0x48]	3096373	1			T3	36		T17	4		T34	8990
valid_sources[0x49]	1366081	1			T3	34		T17	4		T34	9053
valid_sources[0x4a]	2003682	1			T3	37		T17	4		T34	9038
valid_sources[0x4b]	1686113	1			T3	42		T17	9		T34	9204
valid_sources[0x4c]	1362392	1			T3	37		T17	14		T34	8935
valid_sources[0x4d]	3331232	1			T3	41		T17	11		T34	9009
valid_sources[0x4e]	1587026	1			T3	30		T17	8		T34	9066
valid_sources[0x4f]	1449582	1			T3	28		T17	10		T34	8890
valid_sources[0x50]	1340378	1			T3	35		T17	7		T34	8882
valid_sources[0x51]	3328515	1			T3	45		T17	7		T34	9003
valid_sources[0x52]	1345414	1			T3	28		T17	6		T34	8984
valid_sources[0x53]	1426794	1			T3	32		T17	9		T34	8988
valid_sources[0x54]	1338150	1			T3	14		T17	8		T34	9070
valid_sources[0x55]	1354848	1			T3	30		T17	5		T34	8944
valid_sources[0x56]	1349273	1			T3	28		T17	9		T34	9160
valid_sources[0x57]	1461777	1			T3	35		T17	9		T34	8815
valid_sources[0x58]	1440937	1			T3	43		T17	6		T34	9020
valid_sources[0x59]	1345707	1			T3	19		T17	7		T34	9097
valid_sources[0x5a]	1344376	1			T3	37		T17	3		T34	8981
valid_sources[0x5b]	1351160	1			T3	38		T17	7		T34	9064
valid_sources[0x5c]	1534360	1			T3	27		T17	7		T34	8918
valid_sources[0x5d]	1359023	1			T3	22		T17	3		T34	8975
valid_sources[0x5e]	1380882	1			T3	27		T17	8		T34	9165
valid_sources[0x5f]	1503760	1			T3	30		T17	8		T34	9174
valid_sources[0x60]	1350322	1			T3	36		T17	8		T34	9051
valid_sources[0x61]	2213418	1			T3	42		T17	5		T34	9095
valid_sources[0x62]	1987874	1			T3	30		T17	5		T34	8941
valid_sources[0x63]	3338050	1			T3	31		T17	6		T34	9206
valid_sources[0x64]	1434077	1			T3	28		T17	7		T34	9113
valid_sources[0x65]	1345839	1			T3	46		T34	9107		T36	3240
valid_sources[0x66]	1335760	1			T3	25		T17	9		T34	9165
valid_sources[0x67]	1343088	1			T3	24		T34	9027		T36	3429
valid_sources[0x68]	1405037	1			T3	32		T17	6		T34	8951
valid_sources[0x69]	1345806	1			T3	29		T17	9		T34	9199
valid_sources[0x6a]	4181966	1			T3	36		T17	12		T34	9067
valid_sources[0x6b]	2448843	1			T3	31		T17	10		T34	8900
valid_sources[0x6c]	1348151	1			T3	37		T17	7		T34	8961
valid_sources[0x6d]	1342666	1			T3	26		T17	7		T34	9238
valid_sources[0x6e]	1341511	1			T3	39		T17	5		T34	9006
valid_sources[0x6f]	2211835	1			T3	34		T17	7		T34	9006
valid_sources[0x70]	1339524	1			T3	35		T17	5		T34	9101
valid_sources[0x71]	1487213	1			T3	31		T17	11		T34	8992
valid_sources[0x72]	3696955	1			T3	37		T17	4		T34	9152
valid_sources[0x73]	2177293	1			T3	22		T17	5		T34	9051
valid_sources[0x74]	2022584	1			T3	28		T17	8		T34	9039
valid_sources[0x75]	1347065	1			T3	28		T17	12		T34	9025
valid_sources[0x76]	2202709	1			T3	45		T17	12		T34	8967
valid_sources[0x77]	1349539	1			T3	38		T17	6		T34	9014
valid_sources[0x78]	1343950	1			T3	27		T17	10		T34	9133
valid_sources[0x79]	1400908	1			T3	33		T17	10		T34	9058
valid_sources[0x7a]	1344447	1			T3	34		T17	10		T34	8947
valid_sources[0x7b]	1347031	1			T3	37		T17	11		T34	9031
valid_sources[0x7c]	1335151	1			T3	30		T17	9		T34	9031
valid_sources[0x7d]	1374349	1			T3	34		T17	14		T34	9162
valid_sources[0x7e]	1350756	1			T3	35		T17	10		T34	8796
valid_sources[0x7f]	3468968	1			T1	16		T3	28		T17	6
valid_sources[0x80]	1345570	1			T3	41		T17	9		T34	8993

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71311365

1

T1

1

T2

337802

T3

3290

values[0x0]

all_enables

biggest_size

60492180

1

T1

4

T2

310617

T3

673

values[0x1]

all_enables

biggest_size

52005296

1

T2

262023

T3

594

T17

329