Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

261043720

1

T1

11

T2

143427

T3

3778

full_word

183817002

1

T1

5

T2

910442

T3

4557

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	444860412	1			T1	16		T2	234471		T3	8335
auto[TlIntgErrCmd]	99	1			T88	4		T133	4		T134	5
auto[TlIntgErrData]	100	1			T88	3		T133	10		T134	2
auto[TlIntgErrBoth]	111	1			T88	3		T133	6		T134	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230681902

1

T1

1

T2

118949

T3

6067

auto[1]

214178820

1

T1

15

T2

115522

T3

2268

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159368433	1			T2	851691		T3	2777		T17	489
auto[TlIntgErrNone]	partial	auto[1]	101675009	1			T1	11		T2	582583		T3	1001
auto[TlIntgErrNone]	full_word	auto[0]	71313326	1			T1	1		T2	337802		T3	3290
auto[TlIntgErrNone]	full_word	auto[1]	112503644	1			T1	4		T2	572640		T3	1267
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T133	2		T134	2		T145	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T88	3		T133	2		T134	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T134	1		T145	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T88	1		T145	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T88	1		T133	6		T145	2
auto[TlIntgErrData]	partial	auto[1]	40	1			T133	2		T134	2		T145	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T88	2		T133	1		T151	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T133	1		T187	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T88	1		T133	2		T134	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T88	1		T133	3		T134	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T189	1		T184	1		T190	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T88	1		T133	1		T187	2