Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	30089	0	0
entropy_period_rd_A	2147483647	1466	0	0
intr_enable_rd_A	2147483647	2083	0	0
prefix_0_rd_A	2147483647	1479	0	0
prefix_10_rd_A	2147483647	1429	0	0
prefix_1_rd_A	2147483647	1364	0	0
prefix_2_rd_A	2147483647	1595	0	0
prefix_3_rd_A	2147483647	1512	0	0
prefix_4_rd_A	2147483647	1408	0	0
prefix_5_rd_A	2147483647	1393	0	0
prefix_6_rd_A	2147483647	1321	0	0
prefix_7_rd_A	2147483647	1368	0	0
prefix_8_rd_A	2147483647	1239	0	0
prefix_9_rd_A	2147483647	1336	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30089	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	13866	0	0
T53	0	12889	0	0
T82	839242	0	0	0
T88	0	1	0	0
T115	1259	0	0	0
T131	0	56	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	619925	0	0	0
T137	0	173	0	0
T143	0	324	0	0
T145	0	1	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T151	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1466	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	38	0	0
T82	839242	0	0	0
T85	0	28	0	0
T87	0	60	0	0
T88	0	73	0	0
T89	0	19	0	0
T115	1259	0	0	0
T133	0	95	0	0
T135	619925	0	0	0
T145	0	91	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T152	0	6	0	0
T166	0	4	0	0
T167	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2083	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	21	0	0
T82	839242	0	0	0
T85	0	9	0	0
T87	0	48	0	0
T88	0	90	0	0
T100	0	7	0	0
T115	1259	0	0	0
T133	0	122	0	0
T135	619925	0	0	0
T138	0	4	0	0
T139	0	19	0	0
T145	0	201	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T168	0	13	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1479	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	25	0	0
T82	839242	0	0	0
T85	0	10	0	0
T87	0	17	0	0
T88	0	50	0	0
T89	0	19	0	0
T100	0	7	0	0
T115	1259	0	0	0
T133	0	33	0	0
T135	619925	0	0	0
T145	0	89	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	11	0	0
T168	0	4	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	39	0	0
T82	839242	0	0	0
T85	0	13	0	0
T87	0	17	0	0
T88	0	30	0	0
T89	0	20	0	0
T100	0	6	0	0
T115	1259	0	0	0
T133	0	49	0	0
T135	619925	0	0	0
T145	0	106	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	9	0	0
T168	0	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1364	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	33	0	0
T82	839242	0	0	0
T85	0	1	0	0
T87	0	29	0	0
T88	0	43	0	0
T89	0	22	0	0
T100	0	18	0	0
T115	1259	0	0	0
T133	0	41	0	0
T135	619925	0	0	0
T145	0	93	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	4	0	0
T168	0	2	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1595	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	36	0	0
T82	839242	0	0	0
T85	0	26	0	0
T87	0	36	0	0
T88	0	38	0	0
T89	0	17	0	0
T100	0	1	0	0
T115	1259	0	0	0
T133	0	29	0	0
T135	619925	0	0	0
T145	0	79	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	18	0	0
T168	0	15	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	31	0	0
T82	839242	0	0	0
T85	0	15	0	0
T87	0	30	0	0
T88	0	47	0	0
T89	0	20	0	0
T100	0	13	0	0
T115	1259	0	0	0
T133	0	37	0	0
T135	619925	0	0	0
T145	0	85	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	7	0	0
T168	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	23	0	0
T82	839242	0	0	0
T85	0	27	0	0
T87	0	26	0	0
T88	0	53	0	0
T89	0	16	0	0
T100	0	8	0	0
T115	1259	0	0	0
T133	0	47	0	0
T135	619925	0	0	0
T145	0	90	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	11	0	0
T168	0	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1393	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	38	0	0
T82	839242	0	0	0
T85	0	13	0	0
T87	0	45	0	0
T88	0	32	0	0
T89	0	7	0	0
T100	0	13	0	0
T115	1259	0	0	0
T133	0	39	0	0
T135	619925	0	0	0
T145	0	84	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	5	0	0
T168	0	1	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1321	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	17	0	0
T82	839242	0	0	0
T85	0	18	0	0
T87	0	26	0	0
T88	0	28	0	0
T89	0	16	0	0
T100	0	4	0	0
T115	1259	0	0	0
T133	0	38	0	0
T135	619925	0	0	0
T145	0	75	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	4	0	0
T168	0	14	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1368	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	23	0	0
T82	839242	0	0	0
T85	0	13	0	0
T87	0	18	0	0
T88	0	31	0	0
T89	0	36	0	0
T100	0	11	0	0
T115	1259	0	0	0
T133	0	48	0	0
T135	619925	0	0	0
T145	0	85	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	7	0	0
T168	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1239	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	18	0	0
T82	839242	0	0	0
T85	0	19	0	0
T87	0	27	0	0
T88	0	30	0	0
T89	0	17	0	0
T100	0	8	0	0
T115	1259	0	0	0
T133	0	42	0	0
T135	619925	0	0	0
T145	0	87	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	9	0	0
T168	0	13	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1336	0	0
T5	42912	0	0	0
T15	104221	0	0	0
T18	156062	32	0	0
T82	839242	0	0	0
T85	0	10	0	0
T87	0	19	0	0
T88	0	52	0	0
T89	0	16	0	0
T100	0	17	0	0
T115	1259	0	0	0
T133	0	51	0	0
T135	619925	0	0	0
T145	0	104	0	0
T147	207210	0	0	0
T148	16912	0	0	0
T149	200170	0	0	0
T150	91638	0	0	0
T166	0	8	0	0
T168	0	6	0	0