Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257866792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183795792

1

T1

252067

T2

1114

T3

324066

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228298685	1			T1	325253		T2	780		T3	425583
values[0x0]	102545767	1			T1	155037		T2	556		T3	202777
values[0x1]	110818132	1			T1	167342		T2	539		T3	220021

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200544635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

241117949

1

T1

338489

T2

1283

T3

438618

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1324127	1			T2	6		T3	3577		T33	3566
valid_sources[0x01]	1483669	1			T2	6		T3	3359		T33	3430
valid_sources[0x02]	1318548	1			T2	4		T3	3102		T33	3412
valid_sources[0x03]	2339464	1			T2	5		T3	3270		T33	3466
valid_sources[0x04]	2283514	1			T2	8		T3	3325		T33	3254
valid_sources[0x05]	1525143	1			T2	4		T3	2914		T33	3461
valid_sources[0x06]	1411970	1			T2	11		T3	3310		T33	3466
valid_sources[0x07]	3296103	1			T2	8		T3	3567		T33	3406
valid_sources[0x08]	1371940	1			T2	8		T3	3297		T33	3447
valid_sources[0x09]	1324887	1			T2	8		T3	3196		T33	3390
valid_sources[0x0a]	1316074	1			T2	8		T3	3026		T33	3400
valid_sources[0x0b]	1319074	1			T2	9		T3	3439		T33	3418
valid_sources[0x0c]	1318813	1			T2	12		T3	3395		T33	3438
valid_sources[0x0d]	1530368	1			T2	5		T3	3360		T33	3407
valid_sources[0x0e]	1322538	1			T2	9		T3	3440		T33	3430
valid_sources[0x0f]	1313324	1			T2	2		T3	2989		T33	3434
valid_sources[0x10]	1756291	1			T2	7		T3	3306		T33	3357
valid_sources[0x11]	1320647	1			T2	8		T3	3420		T33	3410
valid_sources[0x12]	3681033	1			T2	3		T3	3664		T33	3353
valid_sources[0x13]	2099588	1			T2	6		T3	3420		T33	3392
valid_sources[0x14]	1324692	1			T2	8		T3	3063		T33	3357
valid_sources[0x15]	1477564	1			T2	7		T3	3114		T33	3427
valid_sources[0x16]	1324230	1			T2	8		T3	3144		T33	3308
valid_sources[0x17]	1324017	1			T2	7		T3	3033		T33	3547
valid_sources[0x18]	1311353	1			T2	6		T3	3358		T33	3463
valid_sources[0x19]	3667287	1			T2	8		T3	3500		T33	3413
valid_sources[0x1a]	1315859	1			T2	4		T3	3341		T33	3437
valid_sources[0x1b]	1320302	1			T2	9		T3	3551		T33	3476
valid_sources[0x1c]	1392408	1			T2	5		T3	3596		T33	3447
valid_sources[0x1d]	1319799	1			T2	4		T3	3339		T33	3517
valid_sources[0x1e]	1321619	1			T2	7		T3	3362		T33	3402
valid_sources[0x1f]	2204790	1			T2	4		T3	3205		T33	3426
valid_sources[0x20]	1323662	1			T2	3		T3	3312		T33	3393
valid_sources[0x21]	1338100	1			T2	13		T3	3512		T33	3336
valid_sources[0x22]	1955702	1			T2	11		T3	3014		T33	3436
valid_sources[0x23]	1312943	1			T2	7		T3	3175		T33	3558
valid_sources[0x24]	1317811	1			T2	5		T3	3301		T33	3389
valid_sources[0x25]	2641673	1			T2	12		T3	3234		T33	3536
valid_sources[0x26]	1418550	1			T2	6		T3	3338		T33	3335
valid_sources[0x27]	1313831	1			T2	6		T3	3111		T33	3473
valid_sources[0x28]	1433198	1			T2	11		T3	2935		T33	3501
valid_sources[0x29]	1326161	1			T2	13		T3	3249		T33	3480
valid_sources[0x2a]	1319795	1			T2	11		T3	3310		T33	3448
valid_sources[0x2b]	2232560	1			T2	5		T3	3369		T33	3450
valid_sources[0x2c]	1322301	1			T2	10		T3	2741		T33	3436
valid_sources[0x2d]	1414942	1			T2	7		T3	3255		T33	3471
valid_sources[0x2e]	1411639	1			T2	3		T3	3399		T33	3519
valid_sources[0x2f]	1313203	1			T2	6		T3	3336		T33	3532
valid_sources[0x30]	1358278	1			T2	6		T3	2908		T33	3448
valid_sources[0x31]	1321007	1			T2	9		T3	3493		T33	3452
valid_sources[0x32]	1320349	1			T2	3		T3	3222		T33	3480
valid_sources[0x33]	1794897	1			T2	3		T3	3311		T33	3396
valid_sources[0x34]	1325042	1			T2	14		T3	3192		T33	3377
valid_sources[0x35]	1427134	1			T2	10		T3	3224		T33	3444
valid_sources[0x36]	1315887	1			T2	8		T3	3452		T33	3410
valid_sources[0x37]	1317546	1			T2	11		T3	3293		T33	3384
valid_sources[0x38]	1354491	1			T2	5		T3	3310		T33	3459
valid_sources[0x39]	1350066	1			T2	8		T3	3302		T33	3472
valid_sources[0x3a]	1320834	1			T2	8		T3	3578		T33	3443
valid_sources[0x3b]	2352503	1			T2	9		T3	3120		T33	3386
valid_sources[0x3c]	1317838	1			T2	6		T3	3577		T33	3463
valid_sources[0x3d]	1321226	1			T2	7		T3	3308		T33	3365
valid_sources[0x3e]	1813482	1			T2	3		T3	3042		T33	3496
valid_sources[0x3f]	1315410	1			T2	6		T3	3295		T33	3379
valid_sources[0x40]	1316984	1			T2	2		T3	3313		T33	3391
valid_sources[0x41]	1317103	1			T2	9		T3	3401		T33	3413
valid_sources[0x42]	1319889	1			T2	10		T3	3245		T33	3394
valid_sources[0x43]	1320327	1			T2	5		T3	3264		T33	3385
valid_sources[0x44]	2176278	1			T2	8		T3	3294		T33	3494
valid_sources[0x45]	1312638	1			T2	5		T3	3327		T33	3440
valid_sources[0x46]	1320887	1			T2	11		T3	3372		T33	3307
valid_sources[0x47]	1316894	1			T2	9		T3	3549		T33	3374
valid_sources[0x48]	4342454	1			T2	8		T3	3319		T33	3496
valid_sources[0x49]	1762588	1			T2	4		T3	3286		T33	3412
valid_sources[0x4a]	1588106	1			T2	6		T3	3709		T33	3380
valid_sources[0x4b]	1391228	1			T2	3		T3	3363		T33	3422
valid_sources[0x4c]	1320079	1			T2	8		T3	3630		T33	3333
valid_sources[0x4d]	1441786	1			T2	4		T3	3308		T33	3462
valid_sources[0x4e]	1341758	1			T2	12		T3	3282		T33	3426
valid_sources[0x4f]	1319829	1			T2	3		T3	3112		T33	3450
valid_sources[0x50]	2170092	1			T2	7		T3	3273		T33	3487
valid_sources[0x51]	1319211	1			T2	5		T3	3226		T33	3439
valid_sources[0x52]	3635045	1			T2	11		T3	3281		T33	3435
valid_sources[0x53]	2086472	1			T2	10		T3	3144		T33	3498
valid_sources[0x54]	1319036	1			T2	14		T3	3501		T33	3432
valid_sources[0x55]	4526307	1			T2	5		T3	3349		T33	3448
valid_sources[0x56]	1383041	1			T2	6		T3	3208		T33	3467
valid_sources[0x57]	1320288	1			T2	9		T3	3147		T33	3456
valid_sources[0x58]	1328906	1			T2	9		T3	3020		T33	3379
valid_sources[0x59]	1377116	1			T2	8		T3	3354		T33	3417
valid_sources[0x5a]	3141105	1			T2	5		T3	3465		T33	3410
valid_sources[0x5b]	1324174	1			T2	7		T3	3091		T33	3353
valid_sources[0x5c]	3952320	1			T2	4		T3	3102		T33	3402
valid_sources[0x5d]	1322853	1			T2	6		T3	3436		T33	3522
valid_sources[0x5e]	2781059	1			T2	7		T3	3491		T33	3364
valid_sources[0x5f]	1321953	1			T2	13		T3	3301		T33	3494
valid_sources[0x60]	1321756	1			T2	7		T3	3514		T33	3409
valid_sources[0x61]	1318966	1			T2	12		T3	3388		T33	3444
valid_sources[0x62]	1320444	1			T2	4		T3	3172		T33	3440
valid_sources[0x63]	3291589	1			T2	4		T3	3238		T33	3479
valid_sources[0x64]	1312108	1			T2	11		T3	3258		T33	3352
valid_sources[0x65]	1313690	1			T2	7		T3	3107		T33	3446
valid_sources[0x66]	1475984	1			T2	2		T3	3523		T33	3401
valid_sources[0x67]	1311929	1			T2	3		T3	3653		T33	3400
valid_sources[0x68]	1316625	1			T2	10		T3	3574		T33	3444
valid_sources[0x69]	2227606	1			T2	10		T3	3387		T32	908206
valid_sources[0x6a]	1318447	1			T2	3		T3	3250		T33	3286
valid_sources[0x6b]	1325489	1			T2	3		T3	3219		T33	3447
valid_sources[0x6c]	1315822	1			T2	9		T3	3499		T33	3391
valid_sources[0x6d]	2117721	1			T2	11		T3	3215		T33	3420
valid_sources[0x6e]	1317582	1			T2	15		T3	3078		T33	3354
valid_sources[0x6f]	1321476	1			T2	12		T3	3120		T33	3474
valid_sources[0x70]	1323457	1			T2	8		T3	3632		T33	3463
valid_sources[0x71]	2221139	1			T2	3		T3	3520		T33	3463
valid_sources[0x72]	1321825	1			T2	5		T3	3416		T33	3390
valid_sources[0x73]	1320041	1			T2	8		T3	3583		T33	3479
valid_sources[0x74]	1324449	1			T2	6		T3	3092		T33	3464
valid_sources[0x75]	1970430	1			T1	647632		T2	13		T3	3275
valid_sources[0x76]	1314144	1			T2	8		T3	3513		T33	3358
valid_sources[0x77]	1401323	1			T2	2		T3	3447		T33	3395
valid_sources[0x78]	1318274	1			T2	3		T3	3172		T33	3451
valid_sources[0x79]	1322410	1			T2	4		T3	3444		T33	3411
valid_sources[0x7a]	1449705	1			T2	7		T3	3560		T33	3555
valid_sources[0x7b]	1383547	1			T2	7		T3	3261		T33	3512
valid_sources[0x7c]	1316946	1			T2	8		T3	3269		T33	3407
valid_sources[0x7d]	1343385	1			T2	7		T3	3378		T33	3360
valid_sources[0x7e]	1339652	1			T2	7		T3	3121		T33	3393
valid_sources[0x7f]	1316661	1			T2	3		T3	3244		T33	3372
valid_sources[0x80]	1454607	1			T2	10		T3	3108		T33	3452

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71362139

1

T1

87298

T2

341

T3

111445

values[0x0]

all_enables

biggest_size

60443760

1

T1

89036

T2

398

T3

114920

values[0x1]

all_enables

biggest_size

51989893

1

T1

75733

T2

375

T3

97701