Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

258394856

1

T1

395565

T2

761

T3

524315

full_word

183829283

1

T1

252067

T2

1114

T3

324066

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	442223869	1			T1	647632		T2	1875		T3	848381
auto[TlIntgErrCmd]	78	1			T131	5		T132	6		T133	2
auto[TlIntgErrData]	90	1			T131	6		T132	1		T133	5
auto[TlIntgErrBoth]	102	1			T131	9		T132	3		T133	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228399869

1

T1

325253

T2

780

T3

425583

auto[1]

213824270

1

T1

322379

T2

1095

T3

422798

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157029321	1			T1	237955		T2	439		T3	314138
auto[TlIntgErrNone]	partial	auto[1]	101365291	1			T1	157610		T2	322		T3	210177
auto[TlIntgErrNone]	full_word	auto[0]	71370434	1			T1	87298		T2	341		T3	111445
auto[TlIntgErrNone]	full_word	auto[1]	112458823	1			T1	164769		T2	773		T3	212621
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T131	2		T132	2		T133	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T131	3		T132	4		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T179	2		T180	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T131	3		T133	2		T182	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T131	2		T132	1		T133	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T131	1		T182	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T133	1		T138	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T131	3		T132	1		T133	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T131	6		T132	2		T184	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T182	1		T179	2		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T133	1		T184	1		T185	1