Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	122819	0	0
entropy_period_rd_A	2147483647	1609	0	0
intr_enable_rd_A	2147483647	2575	0	0
prefix_0_rd_A	2147483647	1684	0	0
prefix_10_rd_A	2147483647	1836	0	0
prefix_1_rd_A	2147483647	1890	0	0
prefix_2_rd_A	2147483647	1797	0	0
prefix_3_rd_A	2147483647	1838	0	0
prefix_4_rd_A	2147483647	1796	0	0
prefix_5_rd_A	2147483647	1959	0	0
prefix_6_rd_A	2147483647	1803	0	0
prefix_7_rd_A	2147483647	1829	0	0
prefix_8_rd_A	2147483647	1918	0	0
prefix_9_rd_A	2147483647	1843	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122819	0	0
T24	575932	0	0	0
T25	0	51823	0	0
T48	150722	15969	0	0
T49	0	33606	0	0
T64	198077	0	0	0
T132	0	1	0	0
T139	0	18368	0	0
T140	0	87	0	0
T141	0	174	0	0
T142	0	143	0	0
T143	0	29	0	0
T144	114351	0	0	0
T145	5515	0	0	0
T146	790654	0	0	0
T147	125221	0	0	0
T148	143016	0	0	0
T149	1431	0	0	0
T150	370700	0	0	0
T151	0	181	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1609	0	0
T96	2898	10	0	0
T97	4004	3	0	0
T131	22398	59	0	0
T132	11017	30	0	0
T164	1758	6	0	0
T165	6250	18	0	0
T166	8173	13	0	0
T167	7432	19	0	0
T168	12511	58	0	0
T169	11036	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T97	4004	9	0	0
T131	22398	71	0	0
T132	11017	39	0	0
T135	1774	21	0	0
T164	1758	15	0	0
T165	6250	45	0	0
T166	8173	27	0	0
T170	1219	4	0	0
T171	1893	9	0	0
T172	1439	26	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T96	2898	3	0	0
T97	4004	4	0	0
T131	22398	52	0	0
T132	11017	15	0	0
T164	1758	4	0	0
T165	6250	8	0	0
T166	8173	9	0	0
T167	7432	12	0	0
T168	12511	36	0	0
T173	2107	6	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1836	0	0
T96	2898	15	0	0
T97	4004	3	0	0
T131	22398	45	0	0
T132	11017	20	0	0
T165	6250	21	0	0
T166	8173	7	0	0
T167	7432	11	0	0
T168	12511	42	0	0
T169	11036	7	0	0
T173	2107	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1890	0	0
T96	2898	12	0	0
T97	4004	15	0	0
T131	22398	56	0	0
T132	11017	25	0	0
T164	1758	1	0	0
T165	6250	25	0	0
T166	8173	4	0	0
T167	7432	25	0	0
T168	12511	33	0	0
T173	2107	5	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1797	0	0
T96	2898	3	0	0
T97	4004	4	0	0
T131	22398	55	0	0
T132	11017	13	0	0
T164	1758	3	0	0
T165	6250	43	0	0
T166	8173	25	0	0
T167	7432	21	0	0
T168	12511	51	0	0
T173	2107	4	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1838	0	0
T96	2898	4	0	0
T97	4004	7	0	0
T131	22398	28	0	0
T132	11017	15	0	0
T164	1758	7	0	0
T165	6250	9	0	0
T166	8173	23	0	0
T167	7432	18	0	0
T168	12511	23	0	0
T173	2107	2	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1796	0	0
T97	4004	8	0	0
T131	22398	47	0	0
T132	11017	19	0	0
T164	1758	1	0	0
T165	6250	14	0	0
T166	8173	18	0	0
T167	7432	23	0	0
T168	12511	40	0	0
T169	11036	35	0	0
T173	2107	5	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1959	0	0
T96	2898	14	0	0
T97	4004	15	0	0
T131	22398	51	0	0
T132	11017	7	0	0
T164	1758	5	0	0
T165	6250	6	0	0
T166	8173	12	0	0
T167	7432	12	0	0
T168	12511	33	0	0
T173	2107	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T96	2898	12	0	0
T97	4004	6	0	0
T131	22398	58	0	0
T132	11017	15	0	0
T164	1758	5	0	0
T165	6250	7	0	0
T166	8173	14	0	0
T167	7432	6	0	0
T168	12511	38	0	0
T173	2107	7	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1829	0	0
T96	2898	7	0	0
T97	4004	7	0	0
T131	22398	52	0	0
T132	11017	20	0	0
T164	1758	6	0	0
T165	6250	4	0	0
T166	8173	15	0	0
T167	7432	8	0	0
T168	12511	45	0	0
T173	2107	2	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T96	2898	4	0	0
T97	4004	12	0	0
T131	22398	58	0	0
T132	11017	15	0	0
T164	1758	4	0	0
T165	6250	25	0	0
T166	8173	17	0	0
T167	7432	13	0	0
T168	12511	51	0	0
T173	2107	9	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1843	0	0
T96	2898	5	0	0
T97	4004	6	0	0
T131	22398	51	0	0
T132	11017	22	0	0
T164	1758	5	0	0
T165	6250	24	0	0
T166	8173	12	0	0
T167	7432	12	0	0
T168	12511	36	0	0
T173	2107	6	0	0