Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169094 |
1 |
|
|
T1 |
1862 |
|
T2 |
495 |
|
T7 |
152 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
87438 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
60794 |
1 |
|
|
T1 |
74 |
|
T2 |
14 |
|
T7 |
150 |
seven_bytes |
3011 |
1 |
|
|
T1 |
43 |
|
T2 |
17 |
|
T17 |
39 |
six_bytes |
3023 |
1 |
|
|
T1 |
52 |
|
T2 |
12 |
|
T17 |
32 |
five_bytes |
2987 |
1 |
|
|
T1 |
39 |
|
T2 |
20 |
|
T17 |
32 |
four_bytes |
2946 |
1 |
|
|
T1 |
44 |
|
T2 |
10 |
|
T17 |
47 |
three_bytes |
3032 |
1 |
|
|
T1 |
47 |
|
T2 |
11 |
|
T17 |
36 |
two_bytes |
2971 |
1 |
|
|
T1 |
49 |
|
T2 |
12 |
|
T17 |
34 |
one_byte |
2892 |
1 |
|
|
T1 |
38 |
|
T2 |
8 |
|
T17 |
36 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
165822 |
1 |
|
|
T1 |
1834 |
|
T2 |
489 |
|
T7 |
148 |
auto[1] |
3272 |
1 |
|
|
T1 |
28 |
|
T2 |
6 |
|
T7 |
4 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169094 |
1 |
|
|
T1 |
1862 |
|
T2 |
495 |
|
T7 |
152 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
169086 |
1 |
|
|
T1 |
1861 |
|
T2 |
495 |
|
T7 |
152 |
auto[1] |
8 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T174 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1139 |
1 |
|
|
T1 |
5 |
|
T7 |
2 |
|
T17 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3272 |
1 |
|
|
T1 |
28 |
|
T2 |
6 |
|
T7 |
4 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163617 |
1 |
|
|
T1 |
1992 |
|
T2 |
682 |
|
T17 |
2474 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
79542 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65319 |
1 |
|
|
T1 |
56 |
|
T2 |
17 |
|
T17 |
48 |
seven_bytes |
2697 |
1 |
|
|
T1 |
51 |
|
T2 |
16 |
|
T17 |
65 |
six_bytes |
2703 |
1 |
|
|
T1 |
52 |
|
T2 |
18 |
|
T17 |
64 |
five_bytes |
2620 |
1 |
|
|
T1 |
59 |
|
T2 |
18 |
|
T17 |
64 |
four_bytes |
2753 |
1 |
|
|
T1 |
60 |
|
T2 |
24 |
|
T17 |
71 |
three_bytes |
2672 |
1 |
|
|
T1 |
53 |
|
T2 |
19 |
|
T17 |
68 |
two_bytes |
2602 |
1 |
|
|
T1 |
46 |
|
T2 |
14 |
|
T17 |
61 |
one_byte |
2709 |
1 |
|
|
T1 |
49 |
|
T2 |
23 |
|
T17 |
74 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
160366 |
1 |
|
|
T1 |
1972 |
|
T2 |
674 |
|
T17 |
2446 |
auto[1] |
3251 |
1 |
|
|
T1 |
20 |
|
T2 |
8 |
|
T17 |
28 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163617 |
1 |
|
|
T1 |
1992 |
|
T2 |
682 |
|
T17 |
2474 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163610 |
1 |
|
|
T1 |
1992 |
|
T2 |
682 |
|
T17 |
2474 |
auto[1] |
7 |
1 |
|
|
T175 |
1 |
|
T176 |
1 |
|
T177 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1157 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T17 |
3 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3251 |
1 |
|
|
T1 |
20 |
|
T2 |
8 |
|
T17 |
28 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
345588 |
1 |
|
|
T1 |
5756 |
|
T2 |
1606 |
|
T17 |
3010 |
auto[1] |
589 |
1 |
|
|
T4 |
75 |
|
T8 |
63 |
|
T9 |
33 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
175256 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
129066 |
1 |
|
|
T1 |
160 |
|
T2 |
49 |
|
T17 |
97 |
seven_bytes |
6033 |
1 |
|
|
T1 |
138 |
|
T2 |
44 |
|
T17 |
80 |
six_bytes |
6051 |
1 |
|
|
T1 |
186 |
|
T2 |
54 |
|
T17 |
83 |
five_bytes |
5842 |
1 |
|
|
T1 |
150 |
|
T2 |
39 |
|
T17 |
69 |
four_bytes |
6072 |
1 |
|
|
T1 |
167 |
|
T2 |
38 |
|
T17 |
75 |
three_bytes |
5904 |
1 |
|
|
T1 |
156 |
|
T2 |
36 |
|
T17 |
100 |
two_bytes |
6003 |
1 |
|
|
T1 |
172 |
|
T2 |
39 |
|
T17 |
79 |
one_byte |
5950 |
1 |
|
|
T1 |
150 |
|
T2 |
50 |
|
T17 |
82 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339517 |
1 |
|
|
T1 |
5686 |
|
T2 |
1580 |
|
T17 |
2978 |
auto[1] |
6660 |
1 |
|
|
T1 |
70 |
|
T2 |
26 |
|
T17 |
32 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
346177 |
1 |
|
|
T1 |
5756 |
|
T2 |
1606 |
|
T17 |
3010 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
346148 |
1 |
|
|
T1 |
5755 |
|
T2 |
1606 |
|
T17 |
3010 |
auto[1] |
29 |
1 |
|
|
T1 |
1 |
|
T38 |
1 |
|
T178 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2383 |
1 |
|
|
T1 |
12 |
|
T2 |
5 |
|
T17 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6660 |
1 |
|
|
T1 |
70 |
|
T2 |
26 |
|
T17 |
32 |