Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260434738

1

T1

39293

T2

208499

T3

33772

full_word

185043652

1

T1

59650

T2

177041

T3

274053

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	445478090	1			T1	98943		T2	385540		T3	307825
auto[TlIntgErrCmd]	100	1			T90	5		T106	3		T118	8
auto[TlIntgErrData]	105	1			T90	1		T106	4		T118	6
auto[TlIntgErrBoth]	95	1			T90	4		T106	3		T118	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230735225

1

T1

66334

T2

215401

T3

82310

auto[1]

214743165

1

T1

32609

T2

170139

T3

225515

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159045950	1			T1	24922		T2	127916		T3	30643
auto[TlIntgErrNone]	partial	auto[1]	101388512	1			T1	14371		T2	80583		T3	3129
auto[TlIntgErrNone]	full_word	auto[0]	71689148	1			T1	41412		T2	87485		T3	51667
auto[TlIntgErrNone]	full_word	auto[1]	113354480	1			T1	18238		T2	89556		T3	222386
auto[TlIntgErrCmd]	partial	auto[0]	28	1			T90	3		T118	1		T158	4
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T90	2		T106	3		T118	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T183	1		T184	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T158	1		T180	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T106	2		T118	3		T158	3
auto[TlIntgErrData]	partial	auto[1]	44	1			T90	1		T106	2		T118	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T183	1		T187	1		T188	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T158	1		T181	1		T128	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T90	2		T118	2		T158	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T90	1		T106	3		T118	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T90	1		T189	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T158	1		T184	1		T190	1