Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2877	0	0
entropy_period_rd_A	2147483647	2480	0	0
intr_enable_rd_A	2147483647	3170	0	0
prefix_0_rd_A	2147483647	2390	0	0
prefix_10_rd_A	2147483647	2428	0	0
prefix_1_rd_A	2147483647	2420	0	0
prefix_2_rd_A	2147483647	2492	0	0
prefix_3_rd_A	2147483647	2404	0	0
prefix_4_rd_A	2147483647	2581	0	0
prefix_5_rd_A	2147483647	2381	0	0
prefix_6_rd_A	2147483647	2506	0	0
prefix_7_rd_A	2147483647	2473	0	0
prefix_8_rd_A	2147483647	2388	0	0
prefix_9_rd_A	2147483647	2427	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2877	0	0
T105	3873	3	0	0
T116	2699	269	0	0
T117	5233	93	0	0
T119	7493	124	0	0
T120	3061	8	0	0
T130	5918	106	0	0
T138	3869	1	0	0
T139	6087	5	0	0
T140	3572	3	0	0
T141	2236	1	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2480	0	0
T87	2626	4	0	0
T89	52008	385	0	0
T133	8800	23	0	0
T152	5426	21	0	0
T153	10453	42	0	0
T154	45478	214	0	0
T155	2854	7	0	0
T156	1763	7	0	0
T157	6261	7	0	0
T158	24267	113	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3170	0	0
T87	2626	5	0	0
T89	52008	420	0	0
T152	5426	17	0	0
T153	10453	82	0	0
T154	45478	257	0	0
T155	2854	2	0	0
T156	1763	5	0	0
T159	1281	10	0	0
T160	1368	9	0	0
T161	1645	10	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2390	0	0
T87	2626	4	0	0
T89	52008	403	0	0
T133	8800	19	0	0
T152	5426	15	0	0
T153	10453	18	0	0
T154	45478	200	0	0
T155	2854	7	0	0
T157	6261	6	0	0
T158	24267	76	0	0
T162	11364	27	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2428	0	0
T87	2626	15	0	0
T89	52008	441	0	0
T133	8800	10	0	0
T152	5426	4	0	0
T153	10453	39	0	0
T154	45478	265	0	0
T155	2854	1	0	0
T157	6261	46	0	0
T158	24267	76	0	0
T162	11364	32	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T87	2626	8	0	0
T89	52008	414	0	0
T133	8800	21	0	0
T153	10453	55	0	0
T154	45478	201	0	0
T155	2854	10	0	0
T156	1763	1	0	0
T157	6261	34	0	0
T158	24267	89	0	0
T162	11364	14	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T87	2626	5	0	0
T89	52008	412	0	0
T133	8800	20	0	0
T152	5426	26	0	0
T153	10453	23	0	0
T154	45478	288	0	0
T155	2854	9	0	0
T156	1763	9	0	0
T157	6261	9	0	0
T158	24267	72	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T89	52008	441	0	0
T133	8800	5	0	0
T152	5426	15	0	0
T153	10453	29	0	0
T154	45478	240	0	0
T157	6261	9	0	0
T158	24267	73	0	0
T162	11364	18	0	0
T163	11889	41	0	0
T164	4377	10	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2581	0	0
T87	2626	1	0	0
T89	52008	409	0	0
T129	5238	8	0	0
T133	8800	14	0	0
T152	5426	9	0	0
T153	10453	91	0	0
T154	45478	260	0	0
T157	6261	34	0	0
T158	24267	84	0	0
T162	11364	8	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T89	52008	368	0	0
T133	8800	14	0	0
T134	7096	7	0	0
T152	5426	27	0	0
T153	10453	57	0	0
T154	45478	233	0	0
T155	2854	3	0	0
T157	6261	36	0	0
T158	24267	75	0	0
T162	11364	30	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2506	0	0
T87	2626	6	0	0
T89	52008	438	0	0
T119	7493	4	0	0
T130	5918	5	0	0
T152	5426	11	0	0
T153	10453	27	0	0
T154	45478	252	0	0
T155	2854	2	0	0
T156	1763	4	0	0
T157	6261	6	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T89	52008	373	0	0
T133	8800	10	0	0
T152	5426	10	0	0
T153	10453	40	0	0
T154	45478	200	0	0
T155	2854	13	0	0
T157	6261	20	0	0
T158	24267	83	0	0
T162	11364	16	0	0
T163	11889	29	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2388	0	0
T87	2626	1	0	0
T89	52008	418	0	0
T133	8800	23	0	0
T152	5426	14	0	0
T153	10453	54	0	0
T154	45478	225	0	0
T155	2854	6	0	0
T157	6261	6	0	0
T158	24267	46	0	0
T162	11364	33	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2427	0	0
T87	2626	4	0	0
T89	52008	430	0	0
T133	8800	14	0	0
T152	5426	20	0	0
T153	10453	14	0	0
T154	45478	216	0	0
T155	2854	10	0	0
T156	1763	6	0	0
T157	6261	6	0	0
T158	24267	85	0	0