Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 259481151 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 183161223 1 T1 3112 T2 180245 T3 9770



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 229457996 1 T1 3584 T2 214716 T3 10940
values[0x0] 102488231 1 T1 1120 T2 73612 T3 2673
values[0x1] 110696147 1 T1 1313 T2 73940 T3 2876



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 201777584 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 240864790 1 T1 3770 T2 226900 T3 11325



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 1949917 1 T1 26 T2 1318 T3 70
valid_sources[0x01] 1294904 1 T1 35 T2 1392 T3 75
valid_sources[0x02] 1291190 1 T1 21 T2 1445 T3 62
valid_sources[0x03] 1364606 1 T1 25 T2 1463 T3 68
valid_sources[0x04] 1299660 1 T1 19 T2 1415 T3 80
valid_sources[0x05] 2555676 1 T1 38 T2 1450 T3 68
valid_sources[0x06] 1503547 1 T1 14 T2 1409 T3 69
valid_sources[0x07] 2194988 1 T1 27 T2 1323 T3 73
valid_sources[0x08] 1302286 1 T1 21 T2 1434 T3 62
valid_sources[0x09] 1294767 1 T1 22 T2 1387 T3 79
valid_sources[0x0a] 1294000 1 T1 19 T2 1347 T3 60
valid_sources[0x0b] 3082355 1 T1 30 T2 1342 T3 42
valid_sources[0x0c] 2137465 1 T1 30 T2 1442 T3 73
valid_sources[0x0d] 1290260 1 T1 33 T2 1453 T3 63
valid_sources[0x0e] 1299685 1 T1 26 T2 1404 T3 90
valid_sources[0x0f] 1288747 1 T1 17 T2 1389 T3 57
valid_sources[0x10] 1407862 1 T1 29 T2 1376 T3 56
valid_sources[0x11] 1296212 1 T1 19 T2 1427 T3 55
valid_sources[0x12] 1296984 1 T1 22 T2 1436 T3 54
valid_sources[0x13] 1763956 1 T1 26 T2 1384 T3 61
valid_sources[0x14] 4489513 1 T1 21 T2 1375 T3 67
valid_sources[0x15] 1290428 1 T1 20 T2 1479 T3 66
valid_sources[0x16] 1293688 1 T1 20 T2 1417 T3 51
valid_sources[0x17] 1611380 1 T1 23 T2 1463 T3 59
valid_sources[0x18] 1295664 1 T1 13 T2 1410 T3 60
valid_sources[0x19] 2202303 1 T1 29 T2 1381 T3 63
valid_sources[0x1a] 1337587 1 T1 23 T2 1409 T3 66
valid_sources[0x1b] 3282443 1 T1 36 T2 1370 T3 57
valid_sources[0x1c] 1291785 1 T1 21 T2 1469 T3 63
valid_sources[0x1d] 1292999 1 T1 16 T2 1450 T3 63
valid_sources[0x1e] 1297533 1 T1 28 T2 1488 T3 80
valid_sources[0x1f] 1297153 1 T1 12 T2 1403 T3 61
valid_sources[0x20] 1292531 1 T1 32 T2 1347 T3 70
valid_sources[0x21] 1296560 1 T1 22 T2 1359 T3 69
valid_sources[0x22] 1293465 1 T1 23 T2 1292 T3 69
valid_sources[0x23] 1297641 1 T1 25 T2 1355 T3 48
valid_sources[0x24] 1288829 1 T1 32 T2 1437 T3 62
valid_sources[0x25] 3617686 1 T1 24 T2 1380 T3 64
valid_sources[0x26] 3932003 1 T1 21 T2 1437 T3 56
valid_sources[0x27] 1740534 1 T1 23 T2 1454 T3 72
valid_sources[0x28] 3625926 1 T1 19 T2 1468 T3 73
valid_sources[0x29] 1293857 1 T1 23 T2 1414 T3 58
valid_sources[0x2a] 1755771 1 T1 33 T2 1336 T3 72
valid_sources[0x2b] 1296001 1 T1 25 T2 1368 T3 81
valid_sources[0x2c] 2167513 1 T1 29 T2 1413 T3 50
valid_sources[0x2d] 1303270 1 T1 35 T2 1434 T3 59
valid_sources[0x2e] 1963064 1 T1 17 T2 1425 T3 74
valid_sources[0x2f] 1758052 1 T1 15 T2 1389 T3 58
valid_sources[0x30] 2573574 1 T1 18 T2 1447 T3 69
valid_sources[0x31] 1296843 1 T1 21 T2 1422 T3 60
valid_sources[0x32] 1294097 1 T1 23 T2 1380 T3 69
valid_sources[0x33] 1419680 1 T1 25 T2 1450 T3 67
valid_sources[0x34] 1294954 1 T1 24 T2 1361 T3 56
valid_sources[0x35] 1285675 1 T1 24 T2 1420 T3 52
valid_sources[0x36] 1290944 1 T1 20 T2 1565 T3 71
valid_sources[0x37] 1293198 1 T1 23 T2 1537 T3 81
valid_sources[0x38] 1292889 1 T1 29 T2 1425 T3 60
valid_sources[0x39] 1855248 1 T1 28 T2 1358 T3 63
valid_sources[0x3a] 3256629 1 T1 17 T2 1447 T3 48
valid_sources[0x3b] 1299414 1 T1 22 T2 1400 T3 56
valid_sources[0x3c] 2160200 1 T1 26 T2 1302 T3 99
valid_sources[0x3d] 1296017 1 T1 20 T2 1358 T3 60
valid_sources[0x3e] 2195054 1 T1 26 T2 1305 T3 56
valid_sources[0x3f] 1854074 1 T1 16 T2 1400 T3 64
valid_sources[0x40] 1495443 1 T1 16 T2 1413 T3 72
valid_sources[0x41] 1289914 1 T1 26 T2 1385 T3 66
valid_sources[0x42] 1319586 1 T1 21 T2 1406 T3 52
valid_sources[0x43] 1439246 1 T1 19 T2 1474 T3 55
valid_sources[0x44] 1289358 1 T1 22 T2 1417 T3 73
valid_sources[0x45] 1293707 1 T1 16 T2 1411 T3 54
valid_sources[0x46] 1299609 1 T1 25 T2 1531 T3 74
valid_sources[0x47] 1293473 1 T1 27 T2 1375 T3 84
valid_sources[0x48] 1293939 1 T1 20 T2 1389 T3 65
valid_sources[0x49] 1289412 1 T1 32 T2 1455 T3 48
valid_sources[0x4a] 1297662 1 T1 17 T2 1416 T3 82
valid_sources[0x4b] 1289003 1 T1 20 T2 1418 T3 50
valid_sources[0x4c] 3390234 1 T1 20 T2 1502 T3 77
valid_sources[0x4d] 1291923 1 T1 20 T2 1457 T3 54
valid_sources[0x4e] 1296033 1 T1 28 T2 1464 T3 71
valid_sources[0x4f] 1299542 1 T1 20 T2 1393 T3 64
valid_sources[0x50] 3648664 1 T1 16 T2 1464 T3 62
valid_sources[0x51] 1344130 1 T1 26 T2 1437 T3 63
valid_sources[0x52] 1292774 1 T1 20 T2 1351 T3 67
valid_sources[0x53] 1757834 1 T1 12 T2 1399 T3 63
valid_sources[0x54] 1293697 1 T1 20 T2 1378 T3 87
valid_sources[0x55] 1299691 1 T1 24 T2 1468 T3 68
valid_sources[0x56] 1295148 1 T1 32 T2 1453 T3 65
valid_sources[0x57] 1295396 1 T1 21 T2 1423 T3 64
valid_sources[0x58] 1294495 1 T1 22 T2 1379 T3 67
valid_sources[0x59] 1290387 1 T1 23 T2 1337 T3 65
valid_sources[0x5a] 1295643 1 T1 32 T2 1494 T3 79
valid_sources[0x5b] 1301876 1 T1 18 T2 1425 T3 58
valid_sources[0x5c] 1297129 1 T1 22 T2 1429 T3 67
valid_sources[0x5d] 1748677 1 T1 23 T2 1417 T3 51
valid_sources[0x5e] 1298743 1 T1 23 T2 1517 T3 54
valid_sources[0x5f] 1294379 1 T1 24 T2 1431 T3 49
valid_sources[0x60] 1296324 1 T1 23 T2 1421 T3 69
valid_sources[0x61] 1292007 1 T1 26 T2 1398 T3 51
valid_sources[0x62] 3441474 1 T1 22 T2 1357 T3 59
valid_sources[0x63] 2153306 1 T1 17 T2 1526 T3 58
valid_sources[0x64] 3221501 1 T1 29 T2 1388 T3 77
valid_sources[0x65] 1550398 1 T1 28 T2 1468 T3 50
valid_sources[0x66] 1290722 1 T1 27 T2 1414 T3 80
valid_sources[0x67] 1296919 1 T1 24 T2 1545 T3 78
valid_sources[0x68] 1294010 1 T1 19 T2 1452 T3 58
valid_sources[0x69] 2144473 1 T1 17 T2 1381 T3 56
valid_sources[0x6a] 1301042 1 T1 15 T2 1406 T3 58
valid_sources[0x6b] 1292788 1 T1 19 T2 1445 T3 64
valid_sources[0x6c] 3059895 1 T1 19 T2 1431 T3 54
valid_sources[0x6d] 1520851 1 T1 38 T2 1427 T3 71
valid_sources[0x6e] 1298436 1 T1 25 T2 1513 T3 54
valid_sources[0x6f] 2164814 1 T1 22 T2 1393 T3 51
valid_sources[0x70] 1304337 1 T1 21 T2 1397 T3 70
valid_sources[0x71] 1295327 1 T1 22 T2 1476 T3 60
valid_sources[0x72] 1296403 1 T1 21 T2 1432 T3 53
valid_sources[0x73] 3269085 1 T1 31 T2 1397 T3 81
valid_sources[0x74] 1299111 1 T1 15 T2 1489 T3 48
valid_sources[0x75] 1288925 1 T1 26 T2 1358 T3 68
valid_sources[0x76] 1291764 1 T1 26 T2 1441 T3 61
valid_sources[0x77] 1300293 1 T1 22 T2 1433 T3 84
valid_sources[0x78] 2384530 1 T1 29 T2 1369 T3 70
valid_sources[0x79] 1294815 1 T1 25 T2 1442 T3 51
valid_sources[0x7a] 2158666 1 T1 22 T2 1389 T3 49
valid_sources[0x7b] 1456814 1 T1 17 T2 1442 T3 75
valid_sources[0x7c] 1299878 1 T1 27 T2 1403 T3 74
valid_sources[0x7d] 1474554 1 T1 29 T2 1416 T3 65
valid_sources[0x7e] 1948925 1 T1 20 T2 1369 T3 73
valid_sources[0x7f] 2209000 1 T1 29 T2 1388 T3 68
valid_sources[0x80] 1292843 1 T1 15 T2 1437 T3 55



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 70719424 1 T1 1875 T2 34661 T3 6779
values[0x0] all_enables biggest_size 60447911 1 T1 663 T2 72778 T3 1578
values[0x1] all_enables biggest_size 51993888 1 T1 574 T2 72806 T3 1413

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%