Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259494568

1

T1

2905

T2

182023

T3

6719

full_word

183162053

1

T1

3112

T2

180245

T3

9770

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	442656331	1			T1	6017		T2	362268		T3	16489
auto[TlIntgErrCmd]	105	1			T104	5		T127	2		T128	9
auto[TlIntgErrData]	89	1			T104	9		T127	6		T128	7
auto[TlIntgErrBoth]	96	1			T104	6		T127	2		T128	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229460670

1

T1

3584

T2

214716

T3

10940

auto[1]

213195951

1

T1

2433

T2

147552

T3

5549

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158740928	1			T1	1709		T2	180055		T3	4161
auto[TlIntgErrNone]	partial	auto[1]	100753382	1			T1	1196		T2	1968		T3	2558
auto[TlIntgErrNone]	full_word	auto[0]	70719610	1			T1	1875		T2	34661		T3	6779
auto[TlIntgErrNone]	full_word	auto[1]	112442411	1			T1	1237		T2	145584		T3	2991
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T104	3		T127	2		T128	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T104	2		T128	5		T148	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T148	1		T179	1		T181	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T179	1		T180	1		T182	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T104	6		T127	1		T128	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T104	2		T127	4		T128	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T104	1		T128	1		T180	2
auto[TlIntgErrData]	full_word	auto[1]	3	1			T127	1		T180	1		T183	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T104	3		T148	1		T179	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T104	3		T127	2		T128	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T184	1		T137	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T148	1		T181	1		T185	1