Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	3222	0	0
entropy_period_rd_A	2147483647	964	0	0
intr_enable_rd_A	2147483647	1558	0	0
prefix_0_rd_A	2147483647	819	0	0
prefix_10_rd_A	2147483647	888	0	0
prefix_1_rd_A	2147483647	868	0	0
prefix_2_rd_A	2147483647	959	0	0
prefix_3_rd_A	2147483647	994	0	0
prefix_4_rd_A	2147483647	927	0	0
prefix_5_rd_A	2147483647	1039	0	0
prefix_6_rd_A	2147483647	938	0	0
prefix_7_rd_A	2147483647	978	0	0
prefix_8_rd_A	2147483647	957	0	0
prefix_9_rd_A	2147483647	959	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3222	0	0
T103	8594	126	0	0
T104	19263	2	0	0
T105	7900	5	0	0
T126	2972	52	0	0
T127	5409	1	0	0
T128	23704	2	0	0
T129	9995	367	0	0
T130	2529	98	0	0
T138	6582	78	0	0
T146	4134	28	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	964	0	0
T84	11392	23	0	0
T85	3834	12	0	0
T97	3544	22	0	0
T105	7900	14	0	0
T128	23704	102	0	0
T158	2905	19	0	0
T159	1981	11	0	0
T160	5335	16	0	0
T161	2324	11	0	0
T162	63171	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558	0	0
T84	11392	76	0	0
T85	3834	11	0	0
T97	3544	15	0	0
T105	7900	22	0	0
T134	1738	7	0	0
T158	2905	20	0	0
T159	1981	8	0	0
T160	5335	1	0	0
T161	2324	8	0	0
T163	1336	29	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	819	0	0
T84	11392	33	0	0
T85	3834	14	0	0
T92	5228	7	0	0
T97	3544	12	0	0
T105	7900	6	0	0
T128	23704	79	0	0
T158	2905	2	0	0
T160	5335	16	0	0
T161	2324	8	0	0
T162	63171	129	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	888	0	0
T84	11392	37	0	0
T85	3834	14	0	0
T97	3544	3	0	0
T105	7900	4	0	0
T128	23704	69	0	0
T158	2905	3	0	0
T159	1981	10	0	0
T160	5335	5	0	0
T161	2324	5	0	0
T162	63171	167	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	868	0	0
T84	11392	31	0	0
T85	3834	10	0	0
T97	3544	14	0	0
T105	7900	15	0	0
T128	23704	94	0	0
T158	2905	10	0	0
T159	1981	1	0	0
T160	5335	17	0	0
T161	2324	7	0	0
T162	63171	131	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	959	0	0
T84	11392	41	0	0
T85	3834	17	0	0
T97	3544	13	0	0
T103	8594	8	0	0
T105	7900	13	0	0
T128	23704	85	0	0
T158	2905	13	0	0
T160	5335	1	0	0
T161	2324	9	0	0
T162	63171	153	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	994	0	0
T84	11392	36	0	0
T85	3834	10	0	0
T92	5228	14	0	0
T97	3544	15	0	0
T105	7900	20	0	0
T128	23704	95	0	0
T148	10851	26	0	0
T158	2905	11	0	0
T161	2324	4	0	0
T162	63171	152	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	927	0	0
T84	11392	20	0	0
T85	3834	6	0	0
T97	3544	14	0	0
T105	7900	22	0	0
T128	23704	84	0	0
T158	2905	12	0	0
T159	1981	2	0	0
T160	5335	10	0	0
T161	2324	1	0	0
T162	63171	87	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1039	0	0
T84	11392	24	0	0
T85	3834	16	0	0
T97	3544	5	0	0
T105	7900	27	0	0
T128	23704	76	0	0
T158	2905	13	0	0
T159	1981	9	0	0
T160	5335	16	0	0
T161	2324	5	0	0
T162	63171	151	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	938	0	0
T84	11392	42	0	0
T85	3834	20	0	0
T97	3544	14	0	0
T105	7900	15	0	0
T128	23704	89	0	0
T158	2905	3	0	0
T159	1981	1	0	0
T160	5335	1	0	0
T161	2324	7	0	0
T162	63171	132	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	978	0	0
T84	11392	41	0	0
T85	3834	18	0	0
T97	3544	8	0	0
T105	7900	11	0	0
T128	23704	68	0	0
T158	2905	15	0	0
T159	1981	9	0	0
T160	5335	24	0	0
T161	2324	9	0	0
T162	63171	150	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	957	0	0
T84	11392	30	0	0
T85	3834	9	0	0
T97	3544	9	0	0
T105	7900	13	0	0
T128	23704	91	0	0
T158	2905	4	0	0
T159	1981	3	0	0
T160	5335	18	0	0
T161	2324	5	0	0
T162	63171	118	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	959	0	0
T84	11392	26	0	0
T85	3834	21	0	0
T97	3544	15	0	0
T105	7900	11	0	0
T128	23704	68	0	0
T158	2905	10	0	0
T159	1981	5	0	0
T160	5335	4	0	0
T161	2324	5	0	0
T162	63171	128	0	0