Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	258262713	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182547937

1

T1

99655

T2

462144

T3

249806

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	228010967	1			T1	112699		T2	610458		T3	323655
values[0x0]	102264449	1			T1	29065		T2	257712		T3	153687
values[0x1]	110535234	1			T1	30935		T2	276290		T3	165202

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200788794	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240021856

1

T1

116657

T2

613955

T3

334536

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1311177	1			T1	42		T2	4337		T3	2428
valid_sources[0x01]	1298102	1			T1	46		T2	4605		T3	2456
valid_sources[0x02]	1603167	1			T1	46		T2	4541		T3	2543
valid_sources[0x03]	1951940	1			T1	41		T2	4725		T3	2659
valid_sources[0x04]	2269161	1			T1	40		T2	4608		T3	2629
valid_sources[0x05]	1301999	1			T1	30		T2	4481		T3	2625
valid_sources[0x06]	1384973	1			T1	31		T2	4610		T3	2522
valid_sources[0x07]	1300769	1			T1	48		T2	4214		T3	2509
valid_sources[0x08]	5681098	1			T1	41		T2	4682		T3	2578
valid_sources[0x09]	2157744	1			T1	39		T2	4638		T3	2494
valid_sources[0x0a]	1420774	1			T1	38		T2	4499		T3	2280
valid_sources[0x0b]	2167325	1			T1	40		T2	4480		T3	2341
valid_sources[0x0c]	2489317	1			T1	38		T2	4422		T3	2526
valid_sources[0x0d]	1300967	1			T1	58		T2	4432		T3	2595
valid_sources[0x0e]	1532303	1			T1	41		T2	4530		T3	2427
valid_sources[0x0f]	1301818	1			T1	40		T2	4516		T3	2692
valid_sources[0x10]	1297732	1			T1	47		T2	4308		T3	2505
valid_sources[0x11]	1294949	1			T1	51		T2	4734		T3	2746
valid_sources[0x12]	1304169	1			T1	45		T2	4545		T3	2548
valid_sources[0x13]	1298424	1			T1	45		T2	4461		T3	2347
valid_sources[0x14]	1689187	1			T1	46		T2	4203		T3	2511
valid_sources[0x15]	2207010	1			T1	45		T2	4492		T3	2636
valid_sources[0x16]	1301245	1			T1	52		T2	4526		T3	2349
valid_sources[0x17]	1502596	1			T1	43		T2	4450		T3	2373
valid_sources[0x18]	1294123	1			T1	43		T2	4354		T3	2514
valid_sources[0x19]	1302325	1			T1	38		T2	4572		T3	2551
valid_sources[0x1a]	1304216	1			T1	37		T2	4575		T3	2265
valid_sources[0x1b]	1299127	1			T1	37		T2	4521		T3	2551
valid_sources[0x1c]	1301699	1			T1	36		T2	4295		T3	2461
valid_sources[0x1d]	1304093	1			T1	38		T2	4511		T3	2384
valid_sources[0x1e]	1385496	1			T1	52		T2	4406		T3	2531
valid_sources[0x1f]	1313380	1			T1	41		T2	4411		T3	2475
valid_sources[0x20]	1949943	1			T1	43		T2	4190		T3	2399
valid_sources[0x21]	1300571	1			T1	44		T2	4394		T3	2468
valid_sources[0x22]	2185354	1			T1	49		T2	4387		T3	2429
valid_sources[0x23]	1301271	1			T1	42		T2	4358		T3	2546
valid_sources[0x24]	1294670	1			T1	44		T2	4443		T3	2403
valid_sources[0x25]	1300606	1			T1	42		T2	4288		T3	2482
valid_sources[0x26]	1298751	1			T1	41		T2	4546		T3	2577
valid_sources[0x27]	1441362	1			T1	48		T2	4525		T3	2577
valid_sources[0x28]	1327596	1			T1	42		T2	4456		T3	2455
valid_sources[0x29]	1329824	1			T1	50		T2	4248		T3	2454
valid_sources[0x2a]	1382055	1			T1	52		T2	4459		T3	2517
valid_sources[0x2b]	2367447	1			T1	45		T2	4389		T3	2420
valid_sources[0x2c]	1956164	1			T1	33		T2	4428		T3	2342
valid_sources[0x2d]	1300214	1			T1	53		T2	4403		T3	2570
valid_sources[0x2e]	1298865	1			T1	43		T2	4404		T3	2482
valid_sources[0x2f]	1301523	1			T1	44		T2	4349		T3	2617
valid_sources[0x30]	1296317	1			T1	47		T2	4630		T3	2512
valid_sources[0x31]	1302177	1			T1	41		T2	4194		T3	2431
valid_sources[0x32]	1298568	1			T1	47		T2	4291		T3	2331
valid_sources[0x33]	2254336	1			T1	38		T2	4522		T3	2431
valid_sources[0x34]	1306181	1			T1	49		T2	4493		T3	2610
valid_sources[0x35]	1351847	1			T1	57		T2	4664		T3	2558
valid_sources[0x36]	1299433	1			T1	42		T2	4315		T3	2539
valid_sources[0x37]	1300390	1			T1	49		T2	4227		T3	2610
valid_sources[0x38]	1299704	1			T1	34		T2	4461		T3	2615
valid_sources[0x39]	3605331	1			T1	33		T2	4251		T3	2573
valid_sources[0x3a]	3253888	1			T1	43		T2	4330		T3	2433
valid_sources[0x3b]	1302252	1			T1	29		T2	4367		T3	2494
valid_sources[0x3c]	1302945	1			T1	41		T2	4607		T3	2397
valid_sources[0x3d]	1330465	1			T1	44		T2	4340		T3	2461
valid_sources[0x3e]	2141435	1			T1	44		T2	4481		T3	2799
valid_sources[0x3f]	1303324	1			T1	47		T2	4476		T3	2461
valid_sources[0x40]	1302050	1			T1	44		T2	4548		T3	2552
valid_sources[0x41]	1303114	1			T1	47		T2	4746		T3	2554
valid_sources[0x42]	1301729	1			T1	55		T2	4788		T3	2583
valid_sources[0x43]	2218951	1			T1	44		T2	4662		T3	2331
valid_sources[0x44]	1298369	1			T1	47		T2	4462		T3	2810
valid_sources[0x45]	1297448	1			T1	33		T2	4429		T3	2480
valid_sources[0x46]	3275399	1			T1	53		T2	4323		T3	2490
valid_sources[0x47]	2663089	1			T1	37		T2	4383		T3	2616
valid_sources[0x48]	1297929	1			T1	52		T2	4715		T3	2416
valid_sources[0x49]	1305730	1			T1	43		T2	4550		T3	2614
valid_sources[0x4a]	1306956	1			T1	35		T2	4540		T3	2482
valid_sources[0x4b]	1299203	1			T1	46		T2	4577		T3	2456
valid_sources[0x4c]	1304231	1			T1	51		T2	4830		T3	2447
valid_sources[0x4d]	1300215	1			T1	41		T2	4287		T3	2473
valid_sources[0x4e]	1407895	1			T1	50		T2	4364		T3	2588
valid_sources[0x4f]	1306759	1			T1	39		T2	4310		T3	2608
valid_sources[0x50]	3668164	1			T1	44		T2	4488		T3	2582
valid_sources[0x51]	1362852	1			T1	44		T2	4364		T3	2511
valid_sources[0x52]	1303657	1			T1	48		T2	4607		T3	2481
valid_sources[0x53]	1441515	1			T1	33		T2	4446		T3	2478
valid_sources[0x54]	2229117	1			T1	39		T2	4262		T3	2644
valid_sources[0x55]	1756567	1			T1	46		T2	4469		T3	2566
valid_sources[0x56]	1437890	1			T1	38		T2	4641		T3	2741
valid_sources[0x57]	3638900	1			T1	47		T2	4286		T3	2494
valid_sources[0x58]	3740621	1			T1	41		T2	4347		T3	2380
valid_sources[0x59]	1796770	1			T1	34		T2	4385		T3	2634
valid_sources[0x5a]	1758134	1			T1	40		T2	4341		T3	2413
valid_sources[0x5b]	1555898	1			T1	42		T2	4425		T3	2522
valid_sources[0x5c]	1305996	1			T1	40		T2	4649		T3	2527
valid_sources[0x5d]	1311378	1			T1	39		T2	4320		T3	2568
valid_sources[0x5e]	2118494	1			T1	44		T2	4334		T3	2379
valid_sources[0x5f]	1781118	1			T1	44		T2	4459		T3	2489
valid_sources[0x60]	2212896	1			T1	46		T2	4714		T3	2706
valid_sources[0x61]	1305288	1			T1	53		T2	4474		T3	2377
valid_sources[0x62]	1296364	1			T1	33		T2	4662		T3	2619
valid_sources[0x63]	3725459	1			T1	44		T2	4548		T3	2474
valid_sources[0x64]	3614720	1			T1	54		T2	4512		T3	2443
valid_sources[0x65]	1453824	1			T1	43		T2	4628		T3	2295
valid_sources[0x66]	3634098	1			T1	36		T2	4537		T3	2435
valid_sources[0x67]	1298381	1			T1	47		T2	4347		T3	2453
valid_sources[0x68]	1297558	1			T1	45		T2	4538		T3	2517
valid_sources[0x69]	1319516	1			T1	48		T2	4605		T3	2574
valid_sources[0x6a]	1306666	1			T1	46		T2	4335		T3	2780
valid_sources[0x6b]	3257165	1			T1	48		T2	4390		T3	2492
valid_sources[0x6c]	1309584	1			T1	42		T2	4527		T3	2553
valid_sources[0x6d]	1310620	1			T1	43		T2	4518		T3	2380
valid_sources[0x6e]	1312530	1			T1	42		T2	4823		T3	2654
valid_sources[0x6f]	1299666	1			T1	33		T2	4483		T3	2592
valid_sources[0x70]	3313705	1			T1	39		T2	4212		T3	2568
valid_sources[0x71]	1299614	1			T1	34		T2	4649		T3	2818
valid_sources[0x72]	1760966	1			T1	48		T2	4819		T3	2164
valid_sources[0x73]	1297752	1			T1	32		T2	4600		T3	2590
valid_sources[0x74]	1297589	1			T1	53		T2	4443		T3	2657
valid_sources[0x75]	1298995	1			T1	58		T2	4441		T3	2441
valid_sources[0x76]	1296123	1			T1	52		T2	4273		T3	2486
valid_sources[0x77]	1295731	1			T1	44		T2	4338		T3	2486
valid_sources[0x78]	2246389	1			T1	60		T2	4628		T3	2401
valid_sources[0x79]	1295375	1			T1	40		T2	4382		T3	2540
valid_sources[0x7a]	1299791	1			T1	37		T2	4546		T3	2500
valid_sources[0x7b]	1300886	1			T1	51		T2	4391		T3	2547
valid_sources[0x7c]	1959900	1			T1	34		T2	4217		T3	2407
valid_sources[0x7d]	1297384	1			T1	44		T2	4289		T3	2567
valid_sources[0x7e]	1305573	1			T1	34		T2	4359		T3	2356
valid_sources[0x7f]	1303657	1			T1	38		T2	4594		T3	2444
valid_sources[0x80]	3600409	1			T1	48		T2	4767		T3	2264

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70440198

1

T1

65475

T2

185348

T3

86489

values[0x0]

all_enables

biggest_size

60274553

1

T1

18162

T2

149519

T3

88144

values[0x1]

all_enables

biggest_size

51833186

1

T1

16018

T2

127277

T3

75173