Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

259027702

1

T1

73044

T2

682316

T3

392738

full_word

182596089

1

T1

99655

T2

462144

T3

249806

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	441623501	1			T1	172699		T2	114446		T3	642544
auto[TlIntgErrCmd]	95	1			T136	4		T137	2		T138	12
auto[TlIntgErrData]	89	1			T136	4		T137	5		T138	4
auto[TlIntgErrBoth]	106	1			T136	2		T137	3		T138	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228160970

1

T1

112699

T2

610458

T3

323655

auto[1]

213462821

1

T1

60000

T2

534002

T3

318889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157708444	1			T1	47224		T2	425110		T3	237166
auto[TlIntgErrNone]	partial	auto[1]	101318989	1			T1	25820		T2	257206		T3	155572
auto[TlIntgErrNone]	full_word	auto[0]	70452389	1			T1	65475		T2	185348		T3	86489
auto[TlIntgErrNone]	full_word	auto[1]	112143679	1			T1	34180		T2	276796		T3	163317
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T136	2		T137	1		T138	6
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T136	2		T137	1		T138	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T138	1		T188	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T188	1		T191	1		T192	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T136	4		T137	2		T138	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T137	2		T138	2		T145	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T188	1		T192	1		T193	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T137	1		T194	1		T191	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T137	3		T138	3		T145	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T136	2		T138	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T195	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T145	1		T188	1		T196	1