Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	179174	0	0
entropy_period_rd_A	2147483647	1384	0	0
intr_enable_rd_A	2147483647	1962	0	0
prefix_0_rd_A	2147483647	1388	0	0
prefix_10_rd_A	2147483647	1421	0	0
prefix_1_rd_A	2147483647	1299	0	0
prefix_2_rd_A	2147483647	1259	0	0
prefix_3_rd_A	2147483647	1339	0	0
prefix_4_rd_A	2147483647	1261	0	0
prefix_5_rd_A	2147483647	1335	0	0
prefix_6_rd_A	2147483647	1421	0	0
prefix_7_rd_A	2147483647	1323	0	0
prefix_8_rd_A	2147483647	1332	0	0
prefix_9_rd_A	2147483647	1371	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179174	0	0
T26	583142	80618	0	0
T72	236766	33087	0	0
T79	0	62080	0	0
T136	0	2	0	0
T137	0	2	0	0
T143	0	244	0	0
T144	0	3	0	0
T145	0	1	0	0
T146	0	85	0	0
T147	0	7	0	0
T149	95006	0	0	0
T150	630190	0	0	0
T151	9930	0	0	0
T152	855022	0	0	0
T153	490412	0	0	0
T154	20196	0	0	0
T155	112019	0	0	0
T156	611629	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1384	0	0
T106	11510	75	0	0
T109	12304	79	0	0
T115	4326	6	0	0
T136	12969	59	0	0
T145	10925	24	0	0
T167	6913	23	0	0
T168	51798	401	0	0
T169	11102	28	0	0
T170	2324	5	0	0
T171	6485	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T106	11510	108	0	0
T109	12304	65	0	0
T115	4326	12	0	0
T136	12969	46	0	0
T145	10925	47	0	0
T167	6913	10	0	0
T168	51798	404	0	0
T169	11102	45	0	0
T170	2324	2	0	0
T172	1584	26	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1388	0	0
T106	11510	59	0	0
T109	12304	51	0	0
T115	4326	8	0	0
T136	12969	27	0	0
T145	10925	19	0	0
T167	6913	5	0	0
T168	51798	448	0	0
T169	11102	37	0	0
T170	2324	1	0	0
T171	6485	35	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T106	11510	57	0	0
T109	12304	64	0	0
T115	4326	17	0	0
T136	12969	35	0	0
T145	10925	18	0	0
T167	6913	37	0	0
T168	51798	463	0	0
T169	11102	40	0	0
T170	2324	6	0	0
T171	6485	39	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1299	0	0
T106	11510	65	0	0
T109	12304	50	0	0
T115	4326	8	0	0
T136	12969	38	0	0
T145	10925	11	0	0
T167	6913	16	0	0
T168	51798	398	0	0
T169	11102	35	0	0
T170	2324	8	0	0
T171	6485	20	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259	0	0
T106	11510	60	0	0
T109	12304	22	0	0
T115	4326	7	0	0
T136	12969	17	0	0
T145	10925	22	0	0
T167	6913	33	0	0
T168	51798	430	0	0
T169	11102	40	0	0
T170	2324	6	0	0
T171	6485	3	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1339	0	0
T106	11510	45	0	0
T109	12304	59	0	0
T115	4326	11	0	0
T136	12969	32	0	0
T145	10925	23	0	0
T167	6913	18	0	0
T168	51798	462	0	0
T169	11102	67	0	0
T170	2324	4	0	0
T171	6485	27	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1261	0	0
T106	11510	38	0	0
T109	12304	47	0	0
T115	4326	9	0	0
T136	12969	23	0	0
T145	10925	10	0	0
T167	6913	31	0	0
T168	51798	398	0	0
T169	11102	44	0	0
T171	6485	12	0	0
T173	5976	19	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T106	11510	43	0	0
T109	12304	38	0	0
T115	4326	17	0	0
T136	12969	38	0	0
T145	10925	14	0	0
T167	6913	33	0	0
T168	51798	429	0	0
T169	11102	41	0	0
T170	2324	2	0	0
T171	6485	34	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T106	11510	74	0	0
T109	12304	54	0	0
T115	4326	14	0	0
T136	12969	30	0	0
T145	10925	23	0	0
T167	6913	11	0	0
T168	51798	510	0	0
T169	11102	34	0	0
T171	6485	5	0	0
T173	5976	16	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1323	0	0
T106	11510	42	0	0
T109	12304	48	0	0
T115	4326	9	0	0
T136	12969	25	0	0
T145	10925	19	0	0
T167	6913	19	0	0
T168	51798	396	0	0
T169	11102	73	0	0
T170	2324	1	0	0
T171	6485	18	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1332	0	0
T106	11510	59	0	0
T109	12304	51	0	0
T115	4326	10	0	0
T136	12969	31	0	0
T145	10925	29	0	0
T167	6913	16	0	0
T168	51798	401	0	0
T169	11102	34	0	0
T170	2324	3	0	0
T171	6485	20	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1371	0	0
T106	11510	53	0	0
T109	12304	32	0	0
T115	4326	8	0	0
T136	12969	34	0	0
T145	10925	36	0	0
T167	6913	43	0	0
T168	51798	419	0	0
T169	11102	42	0	0
T170	2324	8	0	0
T171	6485	39	0	0