Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189911 |
1 |
|
|
T8 |
876 |
|
T5 |
2206 |
|
T6 |
1963 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
100261 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
65801 |
1 |
|
|
T8 |
14 |
|
T5 |
2172 |
|
T6 |
1932 |
seven_bytes |
3462 |
1 |
|
|
T8 |
21 |
|
T15 |
68 |
|
T21 |
27 |
six_bytes |
3382 |
1 |
|
|
T8 |
26 |
|
T15 |
51 |
|
T21 |
33 |
five_bytes |
3373 |
1 |
|
|
T8 |
18 |
|
T15 |
54 |
|
T21 |
27 |
four_bytes |
3422 |
1 |
|
|
T8 |
26 |
|
T15 |
52 |
|
T21 |
19 |
three_bytes |
3376 |
1 |
|
|
T8 |
33 |
|
T15 |
66 |
|
T21 |
22 |
two_bytes |
3465 |
1 |
|
|
T8 |
25 |
|
T15 |
58 |
|
T21 |
27 |
one_byte |
3369 |
1 |
|
|
T8 |
16 |
|
T15 |
68 |
|
T21 |
23 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
186303 |
1 |
|
|
T8 |
866 |
|
T5 |
2138 |
|
T6 |
1901 |
auto[1] |
3608 |
1 |
|
|
T8 |
10 |
|
T5 |
68 |
|
T6 |
62 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189911 |
1 |
|
|
T8 |
876 |
|
T5 |
2206 |
|
T6 |
1963 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
189895 |
1 |
|
|
T8 |
876 |
|
T5 |
2206 |
|
T6 |
1962 |
auto[1] |
16 |
1 |
|
|
T6 |
1 |
|
T16 |
1 |
|
T186 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1226 |
1 |
|
|
T5 |
34 |
|
T6 |
31 |
|
T20 |
2 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3608 |
1 |
|
|
T8 |
10 |
|
T5 |
68 |
|
T6 |
62 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
199949 |
1 |
|
|
T8 |
772 |
|
T5 |
1707 |
|
T6 |
1852 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
110626 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
63094 |
1 |
|
|
T8 |
13 |
|
T5 |
1676 |
|
T6 |
1824 |
seven_bytes |
3769 |
1 |
|
|
T8 |
18 |
|
T15 |
29 |
|
T21 |
91 |
six_bytes |
3764 |
1 |
|
|
T8 |
23 |
|
T15 |
22 |
|
T21 |
75 |
five_bytes |
3804 |
1 |
|
|
T8 |
18 |
|
T15 |
31 |
|
T21 |
79 |
four_bytes |
3739 |
1 |
|
|
T8 |
28 |
|
T15 |
22 |
|
T21 |
65 |
three_bytes |
3756 |
1 |
|
|
T8 |
23 |
|
T15 |
37 |
|
T21 |
77 |
two_bytes |
3703 |
1 |
|
|
T8 |
17 |
|
T15 |
39 |
|
T21 |
76 |
one_byte |
3694 |
1 |
|
|
T8 |
10 |
|
T15 |
31 |
|
T21 |
77 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
196258 |
1 |
|
|
T8 |
762 |
|
T5 |
1645 |
|
T6 |
1796 |
auto[1] |
3691 |
1 |
|
|
T8 |
10 |
|
T5 |
62 |
|
T6 |
56 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
199949 |
1 |
|
|
T8 |
772 |
|
T5 |
1707 |
|
T6 |
1852 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
199942 |
1 |
|
|
T8 |
772 |
|
T5 |
1707 |
|
T6 |
1852 |
auto[1] |
7 |
1 |
|
|
T187 |
1 |
|
T188 |
1 |
|
T189 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1225 |
1 |
|
|
T5 |
31 |
|
T6 |
28 |
|
T15 |
7 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3691 |
1 |
|
|
T8 |
10 |
|
T5 |
62 |
|
T6 |
56 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
393237 |
1 |
|
|
T7 |
99 |
|
T8 |
1747 |
|
T5 |
3848 |
auto[1] |
528 |
1 |
|
|
T5 |
64 |
|
T6 |
46 |
|
T9 |
3 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
217699 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
124526 |
1 |
|
|
T7 |
98 |
|
T8 |
47 |
|
T5 |
3848 |
seven_bytes |
7376 |
1 |
|
|
T8 |
63 |
|
T15 |
31 |
|
T21 |
124 |
six_bytes |
7427 |
1 |
|
|
T8 |
61 |
|
T15 |
38 |
|
T21 |
116 |
five_bytes |
7315 |
1 |
|
|
T8 |
51 |
|
T15 |
37 |
|
T21 |
96 |
four_bytes |
7409 |
1 |
|
|
T8 |
51 |
|
T15 |
31 |
|
T21 |
138 |
three_bytes |
7355 |
1 |
|
|
T8 |
37 |
|
T15 |
36 |
|
T21 |
115 |
two_bytes |
7316 |
1 |
|
|
T8 |
44 |
|
T15 |
31 |
|
T21 |
124 |
one_byte |
7342 |
1 |
|
|
T8 |
43 |
|
T15 |
44 |
|
T21 |
99 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
386603 |
1 |
|
|
T7 |
97 |
|
T8 |
1729 |
|
T5 |
3784 |
auto[1] |
7162 |
1 |
|
|
T7 |
2 |
|
T8 |
18 |
|
T5 |
128 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
393765 |
1 |
|
|
T7 |
99 |
|
T8 |
1747 |
|
T5 |
3912 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
393738 |
1 |
|
|
T7 |
99 |
|
T8 |
1747 |
|
T5 |
3912 |
auto[1] |
27 |
1 |
|
|
T44 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2343 |
1 |
|
|
T7 |
1 |
|
T8 |
5 |
|
T5 |
64 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7162 |
1 |
|
|
T7 |
2 |
|
T8 |
18 |
|
T5 |
128 |