Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259728802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184913600

1

T1

9

T2

794233

T3

99280

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230328344	1			T1	1		T2	100883		T3	37076
values[0x0]	102971013	1			T1	12		T2	446305		T3	40530
values[0x1]	111343045	1			T1	22		T2	481304		T3	40962

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201905251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

242737151

1

T1

14

T2

104483

T3

104269

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1316884	1			T2	7752		T3	430		T7	178
valid_sources[0x01]	1314220	1			T2	7667		T3	448		T7	187
valid_sources[0x02]	1908429	1			T2	7690		T3	356		T7	170
valid_sources[0x03]	1326479	1			T2	7442		T3	478		T7	194
valid_sources[0x04]	1960191	1			T2	7569		T3	338		T7	166
valid_sources[0x05]	1369916	1			T2	7630		T3	281		T7	152
valid_sources[0x06]	1325871	1			T2	7780		T3	442		T7	163
valid_sources[0x07]	3298684	1			T2	7497		T3	334		T7	155
valid_sources[0x08]	3293645	1			T2	7611		T3	331		T7	189
valid_sources[0x09]	1344199	1			T2	7701		T3	335		T7	171
valid_sources[0x0a]	1317734	1			T2	7638		T3	362		T7	201
valid_sources[0x0b]	1465517	1			T2	7563		T3	344		T7	182
valid_sources[0x0c]	3125569	1			T2	7763		T3	364		T7	171
valid_sources[0x0d]	2201673	1			T2	7546		T3	338		T7	205
valid_sources[0x0e]	1822502	1			T2	7628		T3	449		T7	166
valid_sources[0x0f]	1316116	1			T1	35		T2	7737		T3	330
valid_sources[0x10]	1319931	1			T2	7488		T3	413		T7	170
valid_sources[0x11]	1320586	1			T2	7553		T3	379		T7	124
valid_sources[0x12]	3675742	1			T2	7590		T3	368		T7	160
valid_sources[0x13]	1323342	1			T2	7537		T3	302		T7	166
valid_sources[0x14]	1328673	1			T2	7557		T3	294		T7	104
valid_sources[0x15]	1361674	1			T2	7665		T3	303		T7	170
valid_sources[0x16]	2300793	1			T2	7623		T3	512		T7	142
valid_sources[0x17]	3270782	1			T2	7720		T3	369		T7	216
valid_sources[0x18]	1318867	1			T2	7546		T3	839		T7	201
valid_sources[0x19]	1319992	1			T2	7550		T3	389		T7	152
valid_sources[0x1a]	1321473	1			T2	7494		T3	287		T7	158
valid_sources[0x1b]	1474154	1			T2	7703		T3	319		T7	191
valid_sources[0x1c]	1340508	1			T2	7642		T3	322		T7	149
valid_sources[0x1d]	1323758	1			T2	7570		T3	471		T7	175
valid_sources[0x1e]	3311448	1			T2	7629		T3	294		T7	167
valid_sources[0x1f]	1320636	1			T2	7775		T3	330		T7	228
valid_sources[0x20]	1314699	1			T2	7561		T3	302		T7	149
valid_sources[0x21]	1766401	1			T2	7489		T3	849		T7	164
valid_sources[0x22]	1319132	1			T2	7555		T3	408		T7	173
valid_sources[0x23]	1325980	1			T2	7706		T3	298		T7	179
valid_sources[0x24]	1319948	1			T2	7650		T3	352		T7	189
valid_sources[0x25]	1962460	1			T2	7758		T3	333		T7	209
valid_sources[0x26]	6267168	1			T2	7470		T3	261		T7	156
valid_sources[0x27]	2656648	1			T2	7521		T3	352		T7	125
valid_sources[0x28]	3325192	1			T2	7857		T3	441		T7	175
valid_sources[0x29]	1320119	1			T2	7437		T3	1428		T7	174
valid_sources[0x2a]	1312704	1			T2	7677		T3	879		T7	153
valid_sources[0x2b]	1506924	1			T2	7624		T3	399		T7	145
valid_sources[0x2c]	2763897	1			T2	7465		T3	805		T7	184
valid_sources[0x2d]	1325796	1			T2	7663		T3	452		T7	169
valid_sources[0x2e]	1322845	1			T2	7471		T3	374		T7	183
valid_sources[0x2f]	1327373	1			T2	7457		T3	854		T7	173
valid_sources[0x30]	1321186	1			T2	7650		T3	541		T7	168
valid_sources[0x31]	1317973	1			T2	7699		T3	1038		T7	166
valid_sources[0x32]	1336376	1			T2	7458		T3	477		T7	170
valid_sources[0x33]	1323302	1			T2	7588		T3	321		T7	152
valid_sources[0x34]	1465838	1			T2	7704		T3	356		T7	189
valid_sources[0x35]	1323950	1			T2	7453		T3	369		T7	141
valid_sources[0x36]	1318987	1			T2	7673		T3	309		T7	145
valid_sources[0x37]	1320999	1			T2	7602		T3	339		T7	127
valid_sources[0x38]	2230492	1			T2	7601		T3	421		T7	176
valid_sources[0x39]	1327710	1			T2	7555		T3	786		T7	158
valid_sources[0x3a]	1320419	1			T2	7615		T3	363		T7	131
valid_sources[0x3b]	1320506	1			T2	7601		T3	412		T7	132
valid_sources[0x3c]	1397078	1			T2	7642		T3	361		T7	165
valid_sources[0x3d]	1337287	1			T2	7518		T3	409		T7	158
valid_sources[0x3e]	1348511	1			T2	7548		T3	329		T7	151
valid_sources[0x3f]	3621629	1			T2	7574		T3	315		T7	184
valid_sources[0x40]	2228685	1			T2	7463		T3	425		T7	208
valid_sources[0x41]	3634668	1			T2	7545		T3	359		T7	165
valid_sources[0x42]	1325189	1			T2	7657		T3	327		T7	199
valid_sources[0x43]	4539620	1			T2	7582		T3	1411		T7	141
valid_sources[0x44]	1315284	1			T2	7758		T3	309		T7	142
valid_sources[0x45]	3290180	1			T2	7846		T3	346		T7	200
valid_sources[0x46]	1352264	1			T2	7420		T3	827		T7	209
valid_sources[0x47]	1314794	1			T2	7590		T3	333		T7	144
valid_sources[0x48]	1327365	1			T2	7564		T3	293		T7	159
valid_sources[0x49]	3315059	1			T2	7467		T3	429		T7	183
valid_sources[0x4a]	1319535	1			T2	7419		T3	613		T7	172
valid_sources[0x4b]	1434581	1			T2	7317		T3	819		T7	124
valid_sources[0x4c]	1316874	1			T2	7447		T3	350		T7	194
valid_sources[0x4d]	3272005	1			T2	7567		T3	355		T7	131
valid_sources[0x4e]	3295653	1			T2	7351		T3	370		T7	185
valid_sources[0x4f]	1325022	1			T2	7553		T3	818		T7	122
valid_sources[0x50]	1316952	1			T2	7952		T3	349		T7	136
valid_sources[0x51]	1775758	1			T2	7532		T3	962		T7	196
valid_sources[0x52]	1326860	1			T2	7550		T3	313		T7	155
valid_sources[0x53]	1318440	1			T2	7546		T3	298		T7	149
valid_sources[0x54]	1328439	1			T2	7061		T3	302		T7	153
valid_sources[0x55]	1326398	1			T2	7601		T3	375		T7	154
valid_sources[0x56]	1317202	1			T2	7578		T3	1095		T7	167
valid_sources[0x57]	1317103	1			T2	7513		T3	350		T7	144
valid_sources[0x58]	1411670	1			T2	7596		T3	1040		T7	168
valid_sources[0x59]	1377180	1			T2	7772		T3	472		T7	169
valid_sources[0x5a]	1325017	1			T2	7653		T3	436		T7	181
valid_sources[0x5b]	1319150	1			T2	7443		T3	332		T7	142
valid_sources[0x5c]	1323576	1			T2	7616		T3	323		T7	152
valid_sources[0x5d]	1323769	1			T2	7451		T3	404		T7	198
valid_sources[0x5e]	1981060	1			T2	7580		T3	357		T7	163
valid_sources[0x5f]	2177227	1			T2	7647		T3	309		T7	159
valid_sources[0x60]	3672335	1			T2	7628		T3	359		T7	174
valid_sources[0x61]	1323796	1			T2	7734		T3	381		T7	147
valid_sources[0x62]	1320881	1			T2	7414		T3	405		T7	112
valid_sources[0x63]	1317104	1			T2	7583		T3	393		T7	191
valid_sources[0x64]	1322505	1			T2	7375		T3	328		T7	234
valid_sources[0x65]	1365099	1			T2	7347		T3	391		T7	187
valid_sources[0x66]	1315805	1			T2	7564		T3	311		T7	189
valid_sources[0x67]	2258719	1			T2	7632		T3	910		T7	159
valid_sources[0x68]	3342434	1			T2	7602		T3	361		T7	185
valid_sources[0x69]	1327442	1			T2	7708		T3	492		T7	169
valid_sources[0x6a]	1321819	1			T2	7504		T3	1025		T7	146
valid_sources[0x6b]	2648970	1			T2	7525		T3	299		T7	187
valid_sources[0x6c]	1321637	1			T2	7461		T3	370		T7	168
valid_sources[0x6d]	1349760	1			T2	7536		T3	459		T7	195
valid_sources[0x6e]	1321454	1			T2	7468		T3	939		T7	195
valid_sources[0x6f]	2274036	1			T2	7403		T3	209		T7	205
valid_sources[0x70]	1323417	1			T2	7569		T3	345		T7	130
valid_sources[0x71]	1323737	1			T2	7586		T3	444		T7	147
valid_sources[0x72]	1484265	1			T2	7701		T3	325		T7	177
valid_sources[0x73]	1314323	1			T2	7547		T3	691		T7	169
valid_sources[0x74]	1319223	1			T2	7735		T3	315		T7	159
valid_sources[0x75]	1770957	1			T2	7507		T3	195		T7	191
valid_sources[0x76]	2145884	1			T2	7647		T3	412		T7	164
valid_sources[0x77]	1323607	1			T2	7472		T3	379		T7	182
valid_sources[0x78]	1314136	1			T2	7681		T3	317		T7	146
valid_sources[0x79]	3563730	1			T2	7673		T3	477		T7	186
valid_sources[0x7a]	3272544	1			T2	7666		T3	287		T7	211
valid_sources[0x7b]	1328195	1			T2	7638		T3	288		T7	170
valid_sources[0x7c]	1318514	1			T2	7731		T3	426		T7	131
valid_sources[0x7d]	1786199	1			T2	7503		T3	361		T7	176
valid_sources[0x7e]	1772282	1			T2	7361		T3	293		T7	172
valid_sources[0x7f]	1319689	1			T2	7604		T3	830		T7	163
valid_sources[0x80]	1988455	1			T2	7316		T3	391		T7	190

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72027106

1

T2

322777

T3

18986

T7

16715

values[0x0]

all_enables

biggest_size

60683320

1

T1

5

T2

255246

T3

40024

values[0x1]

all_enables

biggest_size

52203174

1

T1

4

T2

216210

T3

40270