Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
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Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
93.33 93.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[kmac_reg_block] 93.33 1 100 1 64 64



Group Instance : tl_errors_cgs_wrap[kmac_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
93.33 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[kmac_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 1 14 93.33


Variables for Group Instance tl_errors_cgs_wrap[kmac_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 0 2 100.00 100 1 1 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170672 1 T59 46210 T26 105104 T76 15455
auto[1] 31814 1 T59 8090 T26 20338 T76 2883


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170774 1 T59 45649 T26 105907 T76 15518
auto[1] 31712 1 T59 8651 T26 19535 T76 2820


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 202486 1 T59 54300 T26 125442 T76 18338


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 202400 1 T59 54280 T26 125385 T76 18329
auto[1] 86 1 T59 20 T26 57 T76 9


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192255 1 T59 51511 T26 119137 T76 17388
auto[1] 10231 1 T59 2789 T26 6305 T76 950


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
covered 74525 1 T59 20043 T26 45959 T76 6854


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 196658 1 T59 52788 T26 121794 T76 17809
auto[1] 5828 1 T59 1512 T26 3648 T76 529


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 154280 1 T59 41105 T26 95842 T76 14045
auto[1] 48206 1 T59 13195 T26 29600 T76 4293

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