Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260366970

1

T1

26

T2

114221

T3

19288

full_word

184953549

1

T1

9

T2

794233

T3

99280

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	445320219	1			T1	35		T2	193644		T3	118568
auto[TlIntgErrCmd]	124	1			T141	13		T142	8		T143	2
auto[TlIntgErrData]	80	1			T141	4		T142	4		T143	7
auto[TlIntgErrBoth]	96	1			T141	3		T142	8		T143	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230450781

1

T1

1

T2

100883

T3

37076

auto[1]

214869738

1

T1

34

T2

927609

T3

81492

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158413764	1			T1	1		T2	686059		T3	18090
auto[TlIntgErrNone]	partial	auto[1]	101952923	1			T1	25		T2	456153		T3	1198
auto[TlIntgErrNone]	full_word	auto[0]	72036884	1			T2	322777		T3	18986		T7	16715
auto[TlIntgErrNone]	full_word	auto[1]	112916648	1			T1	9		T2	471456		T3	80294
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T141	4		T142	4		T143	1
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T141	8		T142	4		T143	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T141	1		T190	1		-	-
auto[TlIntgErrData]	partial	auto[0]	35	1			T141	4		T142	2		T143	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T142	2		T143	3		T191	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T143	1		T192	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T191	1		T170	1		T193	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T141	1		T142	5		T143	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T141	2		T142	3		T143	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T190	1		T194	2		T195	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T143	1		T196	1		T190	1