Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.76	98.75	96.74	100.00	100.00	97.06	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	150707	0	0
entropy_period_rd_A	2147483647	1400	0	0
intr_enable_rd_A	2147483647	2376	0	0
prefix_0_rd_A	2147483647	1599	0	0
prefix_10_rd_A	2147483647	1588	0	0
prefix_1_rd_A	2147483647	1619	0	0
prefix_2_rd_A	2147483647	1673	0	0
prefix_3_rd_A	2147483647	1770	0	0
prefix_4_rd_A	2147483647	1689	0	0
prefix_5_rd_A	2147483647	1695	0	0
prefix_6_rd_A	2147483647	1651	0	0
prefix_7_rd_A	2147483647	1667	0	0
prefix_8_rd_A	2147483647	1612	0	0
prefix_9_rd_A	2147483647	1730	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	150707	0	0
T26	0	93192	0	0
T59	488413	40509	0	0
T76	0	13547	0	0
T141	0	3	0	0
T143	0	4	0	0
T147	0	135	0	0
T148	0	216	0	0
T149	0	1	0	0
T150	0	3	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T161	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1400	0	0
T59	488413	89	0	0
T97	0	14	0	0
T98	0	38	0	0
T100	0	57	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	9	0	0
T170	0	23	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	44	0	0
T174	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2376	0	0
T59	488413	95	0	0
T97	0	23	0	0
T98	0	61	0	0
T100	0	40	0	0
T144	0	3	0	0
T145	0	9	0	0
T146	0	9	0	0
T149	0	9	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	7	0	0
T170	0	55	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1599	0	0
T59	488413	97	0	0
T97	0	24	0	0
T98	0	29	0	0
T100	0	35	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	11	0	0
T170	0	22	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	45	0	0
T175	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T59	488413	65	0	0
T97	0	20	0	0
T98	0	41	0	0
T100	0	17	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	4	0	0
T170	0	19	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	40	0	0
T175	0	6	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619	0	0
T59	488413	138	0	0
T97	0	34	0	0
T98	0	39	0	0
T100	0	31	0	0
T103	0	53	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	15	0	0
T170	0	27	0	0
T172	0	9	0	0
T173	0	12	0	0
T174	0	8	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673	0	0
T59	488413	147	0	0
T97	0	24	0	0
T98	0	19	0	0
T100	0	24	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	9	0	0
T170	0	35	0	0
T171	0	9	0	0
T173	0	76	0	0
T174	0	12	0	0
T175	0	12	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1770	0	0
T59	488413	106	0	0
T97	0	22	0	0
T98	0	15	0	0
T100	0	25	0	0
T149	0	7	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	3	0	0
T170	0	38	0	0
T171	0	1	0	0
T172	0	5	0	0
T175	0	1	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1689	0	0
T59	488413	76	0	0
T97	0	17	0	0
T98	0	11	0	0
T100	0	33	0	0
T149	0	18	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	11	0	0
T170	0	10	0	0
T171	0	9	0	0
T173	0	66	0	0
T175	0	6	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1695	0	0
T59	488413	91	0	0
T97	0	18	0	0
T98	0	45	0	0
T100	0	27	0	0
T149	0	1	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	6	0	0
T170	0	28	0	0
T173	0	46	0	0
T174	0	1	0	0
T175	0	4	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1651	0	0
T59	488413	130	0	0
T97	0	15	0	0
T98	0	27	0	0
T100	0	23	0	0
T149	0	4	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T170	0	18	0	0
T171	0	3	0	0
T172	0	5	0	0
T173	0	58	0	0
T175	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1667	0	0
T59	488413	100	0	0
T97	0	18	0	0
T98	0	35	0	0
T100	0	13	0	0
T148	0	1	0	0
T149	0	2	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	7	0	0
T170	0	30	0	0
T171	0	2	0	0
T172	0	3	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612	0	0
T59	488413	83	0	0
T97	0	19	0	0
T98	0	13	0	0
T100	0	16	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	6	0	0
T170	0	32	0	0
T171	0	6	0	0
T172	0	3	0	0
T173	0	69	0	0
T174	0	1	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1730	0	0
T59	488413	83	0	0
T97	0	32	0	0
T98	0	23	0	0
T100	0	33	0	0
T149	0	5	0	0
T152	101755	0	0	0
T153	33157	0	0	0
T154	55051	0	0	0
T155	142169	0	0	0
T156	1682	0	0	0
T157	48134	0	0	0
T158	26536	0	0	0
T159	142470	0	0	0
T160	679578	0	0	0
T169	0	10	0	0
T170	0	24	0	0
T171	0	7	0	0
T172	0	6	0	0
T173	0	28	0	0