Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171253 |
1 |
|
|
T6 |
961 |
|
T7 |
499 |
|
T8 |
480 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
92507 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
56692 |
1 |
|
|
T6 |
26 |
|
T7 |
104 |
|
T8 |
472 |
seven_bytes |
3156 |
1 |
|
|
T6 |
28 |
|
T7 |
11 |
|
T14 |
7 |
six_bytes |
3099 |
1 |
|
|
T6 |
28 |
|
T7 |
9 |
|
T14 |
13 |
five_bytes |
3156 |
1 |
|
|
T6 |
23 |
|
T7 |
12 |
|
T14 |
6 |
four_bytes |
3181 |
1 |
|
|
T6 |
21 |
|
T7 |
10 |
|
T14 |
10 |
three_bytes |
3162 |
1 |
|
|
T6 |
27 |
|
T7 |
16 |
|
T14 |
4 |
two_bytes |
3164 |
1 |
|
|
T6 |
18 |
|
T7 |
9 |
|
T14 |
7 |
one_byte |
3136 |
1 |
|
|
T6 |
32 |
|
T7 |
7 |
|
T14 |
7 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
168053 |
1 |
|
|
T6 |
951 |
|
T7 |
491 |
|
T8 |
464 |
auto[1] |
3200 |
1 |
|
|
T6 |
10 |
|
T7 |
8 |
|
T8 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171253 |
1 |
|
|
T6 |
961 |
|
T7 |
499 |
|
T8 |
480 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171244 |
1 |
|
|
T6 |
961 |
|
T7 |
499 |
|
T8 |
480 |
auto[1] |
9 |
1 |
|
|
T196 |
1 |
|
T197 |
1 |
|
T198 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1066 |
1 |
|
|
T6 |
2 |
|
T7 |
2 |
|
T8 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3200 |
1 |
|
|
T6 |
10 |
|
T7 |
8 |
|
T8 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167657 |
1 |
|
|
T6 |
637 |
|
T7 |
470 |
|
T8 |
519 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
90635 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
55559 |
1 |
|
|
T6 |
15 |
|
T7 |
12 |
|
T8 |
507 |
seven_bytes |
3099 |
1 |
|
|
T6 |
26 |
|
T7 |
13 |
|
T14 |
22 |
six_bytes |
3109 |
1 |
|
|
T6 |
17 |
|
T7 |
9 |
|
T14 |
25 |
five_bytes |
3140 |
1 |
|
|
T6 |
21 |
|
T7 |
14 |
|
T14 |
18 |
four_bytes |
3094 |
1 |
|
|
T6 |
19 |
|
T7 |
14 |
|
T14 |
27 |
three_bytes |
3014 |
1 |
|
|
T6 |
12 |
|
T7 |
6 |
|
T14 |
21 |
two_bytes |
2994 |
1 |
|
|
T6 |
15 |
|
T7 |
11 |
|
T14 |
19 |
one_byte |
3013 |
1 |
|
|
T6 |
20 |
|
T7 |
13 |
|
T14 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
164523 |
1 |
|
|
T6 |
627 |
|
T7 |
462 |
|
T8 |
495 |
auto[1] |
3134 |
1 |
|
|
T6 |
10 |
|
T7 |
8 |
|
T8 |
24 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167657 |
1 |
|
|
T6 |
637 |
|
T7 |
470 |
|
T8 |
519 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
167645 |
1 |
|
|
T6 |
637 |
|
T7 |
470 |
|
T8 |
519 |
auto[1] |
12 |
1 |
|
|
T16 |
1 |
|
T55 |
1 |
|
T199 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1062 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T8 |
12 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3134 |
1 |
|
|
T6 |
10 |
|
T7 |
8 |
|
T8 |
24 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341997 |
1 |
|
|
T6 |
2064 |
|
T7 |
1648 |
|
T8 |
1596 |
auto[1] |
427 |
1 |
|
|
T9 |
92 |
|
T10 |
15 |
|
T11 |
56 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
184357 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
113886 |
1 |
|
|
T6 |
53 |
|
T7 |
297 |
|
T8 |
1574 |
seven_bytes |
6322 |
1 |
|
|
T6 |
49 |
|
T7 |
36 |
|
T19 |
8 |
six_bytes |
6347 |
1 |
|
|
T6 |
53 |
|
T7 |
36 |
|
T19 |
10 |
five_bytes |
6283 |
1 |
|
|
T6 |
66 |
|
T7 |
26 |
|
T19 |
10 |
four_bytes |
6252 |
1 |
|
|
T6 |
56 |
|
T7 |
37 |
|
T19 |
6 |
three_bytes |
6371 |
1 |
|
|
T6 |
54 |
|
T7 |
37 |
|
T19 |
9 |
two_bytes |
6311 |
1 |
|
|
T6 |
56 |
|
T7 |
33 |
|
T19 |
6 |
one_byte |
6295 |
1 |
|
|
T6 |
56 |
|
T7 |
41 |
|
T19 |
7 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336003 |
1 |
|
|
T6 |
2040 |
|
T7 |
1622 |
|
T8 |
1552 |
auto[1] |
6421 |
1 |
|
|
T6 |
24 |
|
T7 |
26 |
|
T8 |
44 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342424 |
1 |
|
|
T6 |
2064 |
|
T7 |
1648 |
|
T8 |
1596 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342405 |
1 |
|
|
T6 |
2063 |
|
T7 |
1648 |
|
T8 |
1596 |
auto[1] |
19 |
1 |
|
|
T6 |
1 |
|
T18 |
1 |
|
T200 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2140 |
1 |
|
|
T6 |
4 |
|
T7 |
6 |
|
T8 |
22 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
6421 |
1 |
|
|
T6 |
24 |
|
T7 |
26 |
|
T8 |
44 |